Memory Controller Voltage Switching for DRAM Power Reduction
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Solution Overview
Problem
Current methods for reducing power consumption in dynamic random access memory (DRAM) increase manufacturing costs and do not substantially decrease power consumption, while also aiming to enhance storage capacity and data transmission speed.
Innovation Solution
A memory system with a controller that includes an analysis module and a switching determination module, which analyzes memory control commands to generate control parameters and determines whether to switch from a normal voltage operation mode to a low voltage operation mode, reducing power consumption without altering manufacturing costs or data transmission speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If advanced process is adopted to achieve low voltage operation, then power consumption is reduced, but manufacturing cost increases
Solution Approach 1:
The patent changes the voltage parameter dynamically by switching between normal voltage mode and low voltage mode based on operation states. The memory controller monitors command types, bank states, and operation modes to determine when to transition voltage levels, thereby reducing power consumption without requiring advanced manufacturing processes.
Solution Approach 2:
The patent implements dynamic voltage switching where the memory system transitions between normal voltage operation mode and low voltage operation mode based on real-time operation states. This dynamic adjustment allows the system to optimize power consumption adaptively without fixed manufacturing constraints.
2Use of energy by moving object
If deep power down mode is provided, then power consumption is reduced, but data transmission speed decreases
Solution Approach 1:
The patent dynamically switches between normal voltage mode and low voltage mode based on operation states, allowing the system to maintain high speed when needed while reducing power consumption during idle or low-activity periods. This avoids the fixed speed reduction associated with deep power down modes.
Solution Approach 2:
The patent changes voltage parameters conditionally rather than transitioning to deep power down mode. By adjusting voltage based on specific operation states (command types, bank states, mode states), the system maintains data transmission speed while achieving power reduction, avoiding the speed penalty of deep power down modes.
3Use of energy by moving object
If input/output capacitance value is lowered, then power consumption is reduced, but manufacturing cost increases
Solution Approach 1:
The patent changes operational voltage parameters through control logic rather than physically altering capacitance values. The memory controller adjusts voltage levels based on operation states, achieving power reduction without requiring manufacturing changes to capacitance components.
4Use of energy by moving object
If data update frequency is altered, then power consumption is reduced, but productivity decreases
Solution Approach 1:
The patent dynamically adjusts voltage based on operation states rather than reducing data update frequency. By switching between normal and low voltage modes conditionally, the system maintains high data transmission bandwidth when needed while reducing power consumption during appropriate states, avoiding productivity loss.
Data Source
AI summary
A memory system comprises a memory controller and a memory device having one or more memory ranks and multiple memory electrically connected to the one or more memory ranks. The memory controller includes at least one analysis module and at least one switching determination module. The analysis module analyzes states of multiple memory control commands corresponding to a particular memory rank to generate a control parameter. The switching determination module determines whether at least one switching command is sent according to the control parameter, a current operation mode of the particular memory rank, and an operation state of the particular memory rank. When the memory device receives a first switching command of the at least one command, the particular rank and at least one part of the memory internal circuits are switched from the normal voltage operation mode to the low voltage operation mode.