Memory Controller Allocating Physical Memory by Wait and Response Levels

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Solution Overview

Problem

In memory systems with a hierarchy of different memory types, existing technologies face challenges in maximizing the utilization efficiency of memory resources when multiple application programs share the same memory hierarchy, as they fail to effectively manage memory access and allocation based on the performance impact of waiting cycles and response times.

Innovation Solution

A memory system and method that includes a memory controller configured to calculate wait levels and response levels of physical memories, using workload monitoring and access statistical information to allocate physical memories to logical memories, thereby optimizing memory allocation and improving resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If memory hierarchy is controlled based on temporal/spatial locality or access frequency, then memory management is simplified, but utilization efficiency of memory resources is not maximized when multiple application programs share the memory hierarchy

Engineering Contradiction:
Improvememory management complexityVSAvoidmemory resource utilization efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent changes the control parameters from simple temporal/spatial locality or access frequency to a comprehensive evaluation system considering wait level, response level, and degree of influence. This allows the memory hierarchy to be controlled based on multiple dynamic parameters that reflect actual system performance impact, thereby maximizing resource utilization efficiency without excessive complexity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where the memory controller continuously monitors wait levels, response levels, and degrees of influence of memory access on processing performance. This feedback information is used to dynamically adjust memory hierarchy control decisions, enabling the system to adapt to changing workload conditions and maximize utilization efficiency

Inventive Principle:
Principle #23Feedback

2Device complexity

If physical memories are allocated without considering wait levels and response levels, then allocation process is simple, but memory access delays increase and resource utilization efficiency decreases

Engineering Contradiction:
Improveallocation process complexityVSAvoidmemory access delay
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent introduces wait level and response level as key parameters for memory allocation decisions. The memory controller calculates these parameters and uses them to determine optimal allocation, changing the allocation criterion from simple first-come-first-served to performance-based allocation that minimizes access delays

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The memory controller performs preliminary calculation of wait levels and response levels before making allocation decisions. This preliminary evaluation allows the system to proactively allocate physical memories in a way that minimizes future access delays, rather than reacting to delays after they occur

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11372560B2Utilization-efficient resource allocation
Publication Date: 2022.06.28 KIOXIA CORP
  • US11372560B2 patent drawing
  • US11372560B2 patent drawing
  • US11372560B2 patent drawing

AI summary

A memory system includes a plurality of physical memories and a memory controller. The memory controller is configured to configure one or more logical memories used by one or more programs, respectively, to which areas of the plurality of physical memories are allocated. The memory controller is configured to calculate first data indicating a response performance of the plurality of physical memories, calculate second data indicating a degree of influence of waiting for access to the one or more logical memories, the degree of influence being on a processing performance of the one or more programs, and control allocation of the areas of the plurality of physical memories to the one or more logical memories on the basis of the first data and the second data.