Memory Controller Parity Recovery for Weak NAND Pages
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Solution Overview
Problem
Existing semiconductor memory devices face issues with weak pages that result in uncorrectable errors, leading to reduced read performance and rapid depletion of usable memory blocks, especially in applications requiring high durability like vehicle systems.
Innovation Solution
A controller generates parity data based on data from weak pages and adjacent pages to recover data efficiently, using an exclusive-OR operation to correct errors and maintain usable memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in weak pages of semiconductor memory device, then memory capacity is increased, but read performance deteriorates due to uncorrectable errors
Solution Approach 1:
The controller performs preliminary actions by generating and storing parity data for weak pages during normal operation. When errors occur during read operations, the controller retrieves the pre-generated parity data to recover corrupted information, thereby maintaining read performance without sacrificing memory capacity
Solution Approach 2:
Parity data acts as an intermediary element between the weak pages and the read operations. The parity data is generated from data in weak pages and adjacent pages, serving as a mediator that enables error correction and data recovery when errors occur, thus resolving the contradiction between storing data in weak pages and maintaining read reliability
2Reliability
If error correction operations are performed repeatedly on weak pages, then data recovery chance is increased, but usable memory blocks deplete rapidly
Solution Approach 1:
The controller generates and stores parity data in advance for weak pages during normal operation. This preliminary action ensures that when errors occur, the controller can immediately use the pre-generated parity data for recovery, reducing the need for repeated error correction operations and extending the usable lifetime of memory blocks
Solution Approach 2:
The controller implements feedback mechanisms by monitoring read operation results and determining whether error correction is needed. When errors are detected in weak pages, the controller uses the stored parity data to recover the information, providing feedback that prevents further degradation of the memory block and extends its usable life
Data Source
AI summary
A controller controls a semiconductor memory device including a plurality of pages. The controller includes a command generator configured to generate a command for controlling a program operation or a read operation of a semiconductor memory device, and a data recovery manager configured to generate parity data corresponding to a weak page among a plurality of pages included in the semiconductor memory device and recover data programmed to the weak page.