Rewritable Non-Volatile Memory Controller Wear Balancing
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Solution Overview
Problem
Existing memory management techniques for rewritable non-volatile memory storage systems face challenges in increasing data writing speed and prolonging the lifespan of memory chips, as physical units wear out unevenly due to limited write cycles and inefficient data relocation within plane-based physical unit groups.
Innovation Solution
A memory management and writing method that groups physical units into two groups, records erase counts, and executes a switched writing procedure when an erase count difference threshold is exceeded, redistributing data across physical unit groups to balance wear and extend the lifespan of memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If physical units are grouped into plane-based physical unit groups for data storage, then data writing speed is improved through copyback instruction sets, but physical units wear out unevenly reducing the lifespan of memory chips
Solution Approach 1:
The patent divides physical units into multiple physical unit groups (first physical unit group and second physical unit group) based on their plane assignments. Each group has its own data area and spare area, enabling independent management and wear balancing across different physical units while maintaining the plane-based structure for efficient data operations.
Solution Approach 2:
The patent introduces erase count tracking as a new parameter for each physical unit and calculates erase count differences between physical unit groups. Based on this parameter, the system dynamically determines whether to execute switched writing procedures, thereby adapting the writing process to balance wear across different physical units and extend overall memory lifespan.
2Quantity of substance
If physical units are alternatively used for storing data through logical unit mapping, then data storage capacity is increased, but physical units experience uneven wear due to limited write cycles
Solution Approach 1:
The patent implements a feedback mechanism where the controller continuously monitors erase counts of physical units and calculates the difference between physical unit groups. Based on this feedback, the system dynamically adjusts the writing process by selecting different physical unit groups for switched writing procedures, thereby balancing wear and extending the overall durability of the memory chip.
Solution Approach 2:
The patent makes the data storage system dynamic by allowing the controller to switch between different physical unit groups based on real-time erase count conditions. The system transitions from static plane-based grouping to dynamic group selection, enabling adaptive wear balancing that extends the usable life of physical units under varying write patterns.
3Speed
If copyback instruction sets are used to move valid old data between physical units, then data relocation speed is improved, but the method is limited to physical units within the same plane
Solution Approach 1:
The patent introduces spare areas as intermediary storage regions between data areas of different physical unit groups. When switched writing procedures need to move data between physical units in different planes, the spare area serves as an intermediate step, enabling data relocation across plane boundaries while maintaining efficient operation through the copyback instruction sets within each group.
Data Source
AI summary
A memory management and writing method for managing a plurality of physical units of a memory chip is provided. The present method includes grouping the physical units into a first physical unit group and a second physical unit group, recording and calculating a first erase count of the first physical unit group and a second erase count of the second physical unit group, and calculating an erase count difference between the first erase count and the second erase count. The present method also includes determining whether the erase count difference is larger than an erase count difference threshold when a write command is received. The method further includes executing a switched writing procedure to write data corresponding to the write command into the memory chip when the erase count difference is larger than the erase count difference threshold. Thereby, the lifespan of the memory chip is effectively prolonged.