Memory Controller Wear Leveling via Segmented Data Distribution
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Solution Overview
Problem
Memory devices, such as NAND flash and PCRAM, have a limited number of write operations before becoming unreliable, leading to uneven service life due to concentrated write operations, which wear leveling methods struggle to address effectively.
Innovation Solution
A memory controller with an address mapping circuit and data distribution circuit that maps logical addresses to physical addresses and determines data distribution patterns across multiple memory devices, adjusting these mappings when specific operations reach a threshold to ensure uniform wear across all devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write operations are concentrated on a specific cell region to simplify data storage, then data access efficiency is improved, but the service life of the memory device is reduced
Solution Approach 1:
The memory system divides data into multiple segments and distributes them across multiple memory devices. Specifically, a page of data is split into multiple pages, with each segment stored in a different memory device. This segmentation allows write operations to be distributed across multiple devices rather than concentrated on one, thereby extending service life while maintaining efficient data access through coordinated management of segmented data.
Solution Approach 2:
Different distribution patterns are applied to different types of data within the same page based on their access characteristics. Normal data and ECC data are distributed using different patterns, with ECC data being distributed to different memory devices than normal data. This local quality approach ensures that frequently updated data types do not always write to the same devices, balancing wear across the system.
2Reliability
If wear leveling is implemented to distribute write operations uniformly, then service life is extended, but data access efficiency deteriorates due to complex address mapping
Solution Approach 1:
The system dynamically adjusts the distribution pattern based on the type of data being written. When normal data is written, one distribution pattern is applied, and when ECC data is written, a different distribution pattern is used. This dynamic adaptation allows the system to optimize for both wear distribution and access efficiency depending on the current write operation, avoiding the need for complex static address mapping while still achieving uniform wear leveling.
Solution Approach 2:
The memory controller implements a universal management mechanism that handles both normal data and ECC data distribution through a unified architecture. The same controller and memory interface manage multiple memory devices, applying different distribution patterns as needed. This multi-functional approach simplifies the overall system compared to separate wear leveling schemes for different data types, maintaining data access efficiency while extending service life.
3Speed
If ECC data and LSB data are stored in specific memory devices to optimize access, then data access speed is improved, but these devices reach wear limit faster
Solution Approach 1:
Different distribution patterns are applied to different types of data within the same page based on their access characteristics. Normal data and ECC data are distributed using different patterns, with ECC data being distributed to different memory devices than normal data. This local quality approach ensures that frequently updated data types do not always write to the same devices, balancing wear across the system.
Solution Approach 2:
The system periodically changes the distribution pattern for ECC data and LSB data across different memory devices. Instead of always writing these data types to the same optimized devices, the pattern rotates or changes over time, distributing the wear burden across all memory devices in the system. This periodic action maintains access efficiency on average while preventing any single device from reaching wear limits prematurely.
Data Source
AI summary
An operating method of a memory controller may include determining a physical page to be accessed in a plurality of memory devices by mapping a logical address to a physical address; and determining a distribution pattern in which data of the physical page are distributed to the plurality of memory devices using the logical address.