Memory Controller WL Bias for 3D NAND Coupling Rise
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Solution Overview
Problem
In three-dimensional memory devices, the channel regions of cell transistors are not directly coupled to the substrate, leading to restricted charge carrier mobility, which results in unintentional voltage changes in word lines due to coupling effects, causing errors in data read operations, especially with increased intervals between read operations or temperature variations.
Innovation Solution
A memory controller implements a WL bias mechanism that applies a positive voltage to word lines during periods of no data read, suppressing the coupling rise effect by maintaining the word line voltage similar to the state with coupling rise, and adjusts based on triggering conditions such as time lapses, read/write counts, and temperature changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If channel regions of cell transistors are not directly coupled to the substrate in three-dimensional memory devices, then device integration and scaling are improved, but charge carrier mobility is restricted causing unintentional voltage changes in word lines
Solution Approach 1:
The patent applies preliminary anti-action by proactively applying a bias voltage to word lines before data read operations to counteract the coupling rise effect. The bias controller detects when a data read operation is about to occur and applies a bias voltage to the selected word line, preemptively compensating for the voltage change that would otherwise occur during the read operation. This prevents the harmful coupling effect from causing data read errors.
2Loss of energy
If word line voltage changes are allowed to occur naturally during no-read periods, then energy consumption is reduced, but coupling rise effects accumulate causing data read errors
Solution Approach 1:
The patent implements periodic action by having the bias controller periodically apply bias voltages to word lines during intervals between data read operations. The controller monitors the elapsed time since the last data read operation and applies bias voltages at predetermined intervals. This periodic compensation prevents the accumulation of coupling rise effects while managing energy consumption through time-based control rather than continuous operation.
Solution Approach 2:
The patent employs feedback mechanisms where the bias controller monitors various parameters including elapsed time since last read operation, temperature changes, and read/write operation counts. Based on this feedback, the controller dynamically determines when to apply bias voltages to word lines, adjusting the compensation strategy according to actual device conditions rather than using fixed continuous application.
3Reliability
If WL bias is applied continuously to suppress coupling rise, then data read reliability is improved, but energy consumption increases
Solution Approach 1:
The patent applies dynamics by making the WL bias application adaptive rather than static. The bias controller dynamically adjusts the bias voltage application based on real-time conditions including elapsed time since last read operation, temperature variations, and operation counts. The system transitions between bias application and non-application states based on current device state, optimizing the balance between reliability and energy consumption.
Solution Approach 2:
The patent utilizes parameter changes by monitoring multiple parameters such as time elapsed since last read operation, temperature, and read/write counts. The bias controller changes the bias voltage parameter based on thresholds of these parameters. For example, when elapsed time exceeds a threshold or temperature changes exceed a threshold, the controller changes the bias voltage state accordingly, providing condition-based compensation.
Data Source
AI summary
According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.