Memory Controller Word Line Staggering for Lower Program Power
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Solution Overview
Problem
Existing memory controllers face challenges in minimizing power consumption during program operations for multiple chips in memory devices, particularly when using quad-level cells, which can exceed designed power limits and affect performance.
Innovation Solution
A memory controller that generates and transmits program commands to start the operation at different starting word lines in multiple target blocks, dispersing the power consumption and maintaining intervals between programmed word lines, thereby reducing overall power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If program operation is performed on multiple chips simultaneously at the same word line positions, then programming efficiency is improved, but power consumption exceeds designed limits
Solution Approach 1:
The patent segments the word line positions into different groups across multiple chips. Instead of programming all chips at the same word line positions simultaneously, the controller assigns different starting word line positions to different chips, dividing the simultaneous programming operation into staggered segments that reduce peak power consumption while maintaining overall programming efficiency
Solution Approach 2:
The patent applies local quality by making each chip's programming operation unique in terms of starting word line position. Each chip is programmed with locally optimized parameters (different starting positions) rather than using a uniform global approach, allowing power distribution to be balanced across the system while maintaining high programming throughput
2Ease of operation
If program operation starts at the same word line position in all target blocks, then operation simplicity is maintained, but power consumption is not minimized
Solution Approach 1:
The patent introduces dynamic adjustment of starting word line positions based on chip identification. The memory controller dynamically determines and assigns different starting positions to different chips rather than using a static uniform starting position, enabling power optimization while the memory device automatically handles the complexity through its internal architecture
Data Source
AI summary
A memory controller controlling a memory device includes a plurality of chips. An operation method of the memory controller includes generating a first program command including information on a plurality of starting word lines at different positions in a plurality of target blocks corresponding to the plurality of chips, and transmitting the first program command to the memory device.