Memory Controller Write Arbitration for Power-Constrained Macros
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Solution Overview
Problem
Memory devices face errors during write operations due to insufficient power supplied by the power circuit, leading to incorrect data writing into memory macros, as the power circuit can only support a limited number of macros being written simultaneously.
Innovation Solution
Implementing a write arbitration technique that detects the number of memory macros being written at the same time and compares it to a predetermined threshold, re-scheduling write operations to ensure that only the maximum number supported by the power circuit are written simultaneously, using a controller to manage this process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of memory macros being written simultaneously is increased to improve productivity, then the write operation throughput is improved, but the power circuit cannot provide sufficient power leading to write errors
Solution Approach 1:
The patent implements dynamic scheduling of write operations where the controller adjusts the number of simultaneous write operations based on power availability and circuit conditions. The write arbitration logic dynamically selects which memory macros receive write operations at each time interval, changing the operational state based on real-time conditions rather than using a fixed allocation scheme.
Solution Approach 2:
The patent divides write operations into discrete time intervals or cycles, where in each interval a controlled number of write operations are performed. The scheduler operates periodically to allocate write operations to different memory macros across successive intervals, ensuring power consumption remains within limits while maintaining overall throughput.
2Reliability
If write operations are limited to the maximum number supported by the power circuit to ensure reliability, then write errors are reduced, but the write operation throughput decreases
Solution Approach 1:
The patent implements a write scheduler that performs preliminary allocation and arbitration of write operations before they are executed. The controller pre-determines which memory macros will receive write operations in upcoming time intervals based on current power availability and circuit conditions, allowing optimal utilization of power capacity without exceeding limits during actual write operations.
Solution Approach 2:
The patent maintains continuous write operations across multiple time intervals by the scheduler ensuring that write operations are continuously allocated to different memory macros without idle periods. The arbitration logic continuously monitors power availability and adjusts allocation to maintain maximum sustainable throughput while ensuring each individual write operation receives sufficient power.
3Productivity
If multiple memory macros are written simultaneously to improve productivity, then the write operation throughput is improved, but power consumption increases beyond the power circuit capacity
Solution Approach 1:
The patent segments the write operation workload across multiple memory macros and time intervals. Instead of concentrating all write operations on a single macro or executing them simultaneously, the scheduler divides the write traffic into manageable segments that are distributed to different memory macros in different time intervals, ensuring power consumption at any moment remains within circuit capacity.
Solution Approach 2:
The patent dynamically changes operational parameters including the number of simultaneous write operations, the selection of target memory macros, and the timing of write operations. The write arbitration logic adjusts these parameters based on power availability and circuit conditions to optimize the balance between throughput and power consumption.
Data Source
AI summary
A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.