Memory Controller With Virtual Bank Addressing for Write Bandwidth
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Solution Overview
Problem
Existing memory systems face challenges in maximizing write bandwidth while maintaining data integrity, particularly in high capacity memory circuits with long write latencies and potential bank conflicts.
Innovation Solution
A memory controller implementing a write staging buffer that cooperates with a write queue to manage write requests, prioritizing commands to different memory banks and minimizing bank conflicts through a staging scheme that includes eviction rules to maximize write bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write requests are issued to memory banks without a staging buffer, then the memory system operates with simpler control logic, but write bandwidth is reduced due to bank conflicts and long write latencies
Solution Approach 1:
The write staging buffer pre-processes and stages write requests before they are issued to memory banks. The control circuit prepares write commands in advance, organizes them by target bank, and stages them for optimal issuance timing, thereby resolving bank conflicts before they occur and maximizing write bandwidth without proportionally increasing control complexity
Solution Approach 2:
The write staging buffer divides write requests into segments corresponding to different memory banks. By separating and independently managing write requests for each bank, the control circuit can issue writes to multiple banks in parallel, reducing bank conflicts and improving overall write bandwidth while maintaining manageable control logic through modular bank-specific handling
2Productivity
If multiple write requests are issued to the same memory bank concurrently, then the control logic is simplified, but bank conflicts increase reducing write bandwidth
Solution Approach 1:
The write staging buffer acts as an intermediary between the host interface and memory banks. It receives write requests, determines the target bank for each request, and stages them appropriately before issuance. This intermediary layer simplifies bank conflict management by automatically routing requests to appropriate banks and timing their issuance to avoid conflicts, without requiring complex control logic at the host interface
Solution Approach 2:
The write staging buffer dynamically adjusts the issuance timing of write requests based on the current state of memory banks. It monitors bank availability and dynamically schedules write commands to be issued when banks are free, thereby eliminating bank conflicts while maintaining simple control logic through adaptive, state-dependent scheduling
3Reliability
If write operations are performed without a staging scheme, then the control circuit is simpler, but data integrity may be compromised during concurrent operations
Solution Approach 1:
The write staging buffer implements feedback mechanisms to track the status of write operations and memory bank availability. It monitors whether writes have been completed or are in progress, and uses this feedback information to determine when it is safe to issue subsequent write requests to the same bank. This feedback-based approach ensures data integrity by preventing premature overwrites while maintaining simple control logic through automated status tracking
Data Source
AI summary
A memory system includes a memory device including an array of storage transistors organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, a command selector to select one or more commands issued by the read queue or the write queue, and a virtual to physical address translator to convert the memory address of the selected command encoded with the virtual bank index to a corresponding memory physical addresses, the selected command with the memory physical address being issued to the memory device for execution at the memory device.