Memory Controller Dynamic Write Driver Adjustment for Resistive Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current nonvolatile memory devices face challenges in optimizing program speed and reducing power consumption, particularly in managing the number of write drivers based on the operational status of NAND flash memory devices and resistive memory devices.
Innovation Solution
A memory controller method that dynamically adjusts the number of write drivers in a resistive memory device based on the busy status of NAND flash memory devices, allowing for efficient data programming by selecting the appropriate number of write drivers to match the operational load, thereby optimizing program speed and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a larger number of write drivers are driven in the resistive memory device, then program speed is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the number of write drivers activated in the resistive memory device based on the operational status of NAND flash memory devices. When NAND flash devices are busy, fewer write drivers are activated to reduce power consumption; when NAND flash devices are idle, more write drivers are activated to improve program speed. This dynamic adaptation resolves the contradiction between speed and power consumption.
Solution Approach 2:
The system changes the operational parameter (number of active write drivers) based on the busy status of NAND flash memory devices. By monitoring whether NAND flash devices are busy or idle, the system adjusts the write driver activation count, thereby optimizing the balance between program speed and power consumption under different operational conditions.
2Adaptability or versatility
If the number of write drivers is fixed, then device complexity is reduced, but adaptability to varying operational loads decreases
Solution Approach 1:
The system implements a feedback mechanism where the memory controller monitors the busy status of NAND flash memory devices and uses this information to determine the appropriate number of write drivers to activate in the resistive memory device. This feedback loop enables the system to adapt to varying operational loads while maintaining relatively simple control logic, as the decision rule is straightforward: adjust write driver count based on NAND flash busy status.
Data Source
AI summary
The present inventive concept provides a driving method of memory controller controlling nonvolatile memory device using variable resistive element. The memory controller may control a plurality of first memory devices and a second memory device. A number of write drivers in the second memory device may be driven when a number of first memory devices among the plurality of first memory devices are used. A different number of write drivers in the second memory device may be driven when a different number of first memory devices among the plurality of first memory devices are used.


