Memory Controller Write Failure Handling via Microcontroller Migration
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Solution Overview
Problem
Existing non-volatile memory systems face challenges in optimizing access and management performance due to latency issues and complex management operations, which hinder efficient utilization of faster access times and storage capabilities.
Innovation Solution
A microcontroller and memory controller architecture is implemented, where the microcontroller manages migration events and handles complex operations, while the memory controller performs reads and writes, using techniques like wear-leveling and address translation to optimize access and reduce latency, allowing for byte addressable storage and efficient data migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If non-volatile memory is used to increase storage capacity and access speed, then storage capacity and access speed are improved, but latency issues and complex management operations worsen performance optimization
Solution Approach 1:
The patent segments the memory management system into distinct components: a memory controller handling basic read/write operations and a separate management unit handling complex operations like wear-leveling and address translation. This segmentation allows each component to specialize in specific tasks, reducing overall system complexity while maintaining high access speeds.
Solution Approach 2:
The patent introduces an address translation layer as an intermediary between the host system and the non-volatile memory. This translation layer handles complex address mapping and wear-leveling operations, allowing the memory controller to focus on fast data access while the intermediary manages the complexity of memory management tasks.
2Reliability
If complex management operations like wear-leveling are implemented, then reliability and data integrity are improved, but access latency increases
Solution Approach 1:
The patent implements preliminary action by performing wear-leveling migrations in the background before they are needed. The system proactively moves data between memory locations to distribute wear evenly, so that when data needs to be accessed, it is already in an optimal location, avoiding latency during actual access operations.
Solution Approach 2:
The patent maintains continuity of useful action by implementing background threads that continuously perform wear-leveling and data migration operations without interrupting foreground read/write operations. This allows reliability improvements to be made continuously without adding latency to data access paths.
3Ease of operation
If byte addressable storage is implemented for granular data access, then ease of operation and data accessibility are improved, but device complexity and management overhead increase
Solution Approach 1:
The patent implements self-service by enabling the memory system to automatically handle byte-addressable access requests through its address translation layer. The system self-manages the mapping between byte-addressable logical addresses and physical memory locations, eliminating the need for external complex management while providing easy byte-level access to users.
Data Source
AI summary
Failed write handling can be implemented at a memory controller for non-volatile memory. Failure of a write to a storage location in the non-volatile memory may be detected. An indication of the failure may be sent to a microcontroller for the non-volatile memory which may return an instruction to write to a different location in the non-volatile memory. Reads and writes to the storage location of the failed write may still be allowed, in some embodiments, by redirecting the reads and writes to a copy of data of the failed write stored in a copy buffer in the memory controller.