Memory Controller Write Leveling Calibration
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Solution Overview
Problem
Conventional DDR SDRAMs require separate programming and storage of multiple start points for DQS strobe signals at higher frequencies, which is time-consuming and inflexible, limiting the ability to accommodate different memory devices and upgrades without recalculating start values.
Innovation Solution
A memory system and method that calibrate per-byte start values for write leveling, using a memory controller to determine and store only one start value, allowing the internal circuitry to calculate start times for other devices based on read calibration, reducing programming complexity and enabling flexibility in memory device upgrades.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate programming and storage of multiple start points for DQS strobe signals is performed at higher frequencies, then data transfer accuracy is improved, but programming time and complexity increase
Solution Approach 1:
The patent segments the memory devices into a prime device and non-prime devices, allowing different calibration approaches for each group. The prime device receives manually programmed start values, while non-prime devices automatically inherit calibrated start values through skew compensation, eliminating the need to program every device individually.
Solution Approach 2:
The system performs self-calibration by having non-prime memory devices automatically determine their own start values based on the prime device's calibrated start value and measured skew. This self-service mechanism eliminates manual programming for each device, reducing programming time while maintaining accuracy.
2Measurement precision
If separate programming and storage of multiple start points for DQS strobe signals is performed, then data transfer accuracy is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal calibration approach where the prime device's calibrated start value serves as a template for all non-prime devices. The memory controller uses a single calibration result combined with skew measurements to determine start values for multiple devices, making the system more versatile and easier to program.
Solution Approach 2:
The system incorporates feedback through skew measurement, where the memory controller measures the actual skew between the prime device and non-prime devices, then uses this feedback to calculate accurate start values for non-prime devices. This feedback mechanism simplifies programming by automatically adjusting for individual device characteristics.
3Measurement precision
If manual calculation and programming of start values for each memory device is performed, then data transfer accuracy is improved, but adaptability to memory upgrades decreases
Solution Approach 1:
The patent implements a dynamic calibration system where start values are not fixed but can be automatically adjusted based on measured skew. This dynamic approach allows the system to adapt to different memory devices and configurations without requiring manual reprogramming, enhancing flexibility for upgrades.
Solution Approach 2:
The system changes the parameter approach from fixed manually-programmed start values to dynamically calculated start values based on measured skew. This parameter change enables the system to automatically adapt to different memory devices, making it more versatile for upgrades and configurations.
Data Source
AI summary
A memory controller performs a read test for each of a plurality of memory devices to generate a read delay time of each memory device. There is a prime memory device and a subset of memory devices. For each memory device of the subset, the read delay time for the prime memory device is compared with the read delay time of each memory device of the subset of memory devices to generate a differential delay for each memory device of the subset. For each subset memory device, a write test start time of the prime memory device is combined with a differential delay of each memory device to generate a write test start time for the each memory device. A write test for each memory device uses the write test start time for each subset memory device to generate a write launch time for each subset memory device.