Memory Controller Write Mode Selection for SSD Performance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory systems, such as solid state drives (SSDs), face challenges in optimizing write performance when transitioning to a suspend state or when data write needs to be completed in the shortest time, often resulting in suboptimal write performance due to the selection of write formats based on internal conditions.
Innovation Solution
A memory system with a controller that selects between single level cell (SLC) and triple level cell (TLC) write modes based on the capacity of the write data and the free area of the nonvolatile memory, prioritizing SLC mode for faster data writing, and employing a strategy to divide the memory into fixed SLC and SLC/TLC switch areas to optimize write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory system selects write format based on internal conditions (dispersed data conditions, friction conditions), then the write format selection adapts to internal state, but the write performance cannot be exerted when host transitions to suspend state or when data write needs to be completed in shortest time
Solution Approach 1:
The patent implements dynamic write format selection by introducing a mode determination unit that switches between normal mode and urgent mode based on real-time analysis of host commands and internal conditions. In normal mode, the system adapts write format to internal conditions (dispersed data, friction). In urgent mode (detected via suspend transition commands or specific write commands), the system prioritizes write speed by selecting optimal write formats regardless of internal state, thus resolving the contradiction between adaptability and productivity.
2Speed
If the memory system uses SLC mode for writing data, then the write speed is faster, but the storage capacity per unit area is reduced (N bits vs M bits)
Solution Approach 1:
The patent segments the storage medium into multiple regions with different write formats (SLC regions and TLC regions). The mode determination unit dynamically selects which region to write to based on the urgentness of the write operation. For urgent writes requiring maximum speed, the system directs data to SLC regions. For non-urgent writes, the system utilizes TLC regions to maximize storage capacity. This segmentation allows the system to achieve fast write speeds when needed while maintaining high storage capacity overall.
3Productivity
If the memory system prioritizes writing data in the shortest time, then the write performance is maximized, but the storage capacity utilization is reduced due to preferring SLC mode
Solution Approach 1:
The patent changes the operational parameters of the storage system by introducing an urgent mode parameter that overrides normal write format selection logic. When urgent mode is activated (detected through suspend transition commands or specific write commands), the system parameter shifts from capacity-optimized format selection to speed-optimized format selection. This parameter change allows the system to achieve maximum write throughput when needed while maintaining high storage capacity utilization during normal operations by returning to adaptive format selection.
Data Source
AI summary
According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory is correspond to a first mode of writing data of N bits per unit area and a second mode of writing data of M bits (M>N) per unit area. When receiving a first command issued prior to a write command to instruct writing write data to the nonvolatile memory, the controller selects one or both of the first mode and the second mode for writing the write data to the nonvolatile memory, to allow writing the write data to the nonvolatile memory to be executed in the first mode as much as possible, based on a capacity of the write data specified by the first command and a capacity of a free area of the nonvolatile memory.


