Memory Controller Write Request Prioritization for Variable Latency
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Solution Overview
Problem
Conventional memory controllers struggle to shorten writing time in storage devices using nonvolatile memory, such as ReRAM, where writing times vary significantly across different access units due to differing physical properties of storage elements and increased verification needs, leading to inefficient command processing.
Innovation Solution
A memory controller with a writing time prediction information holding unit and a request selecting unit that prioritizes write requests based on predicted longer writing times, using measured writing times, verification counts, and error correction data to optimize the order of write requests across multiple memory modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification and rewriting are performed multiple times for nonvolatile memory cells with higher writing frequency, then writing reliability is improved, but writing time increases
Solution Approach 1:
The system performs preliminary verification and rewriting operations for nonvolatile memory cells before they are fully written. By anticipating which memory cells will require multiple verification cycles based on their physical properties and writing frequency, the system executes these operations in advance, thereby improving writing reliability without significantly increasing total writing time.
2Productivity
If command issuing order is controlled to handle stand-by time in SDRAM, then command processing speed is improved, but writing time cannot be shortened in storage devices using nonvolatile memory with variable writing times
Solution Approach 1:
The system dynamically adjusts the command issuing order based on real-time information about memory cell states, verification requirements, and predicted writing times. Unlike static command scheduling, this dynamic approach allows the system to adapt to varying writing time requirements of different nonvolatile memory cells, thereby shortening overall writing time while maintaining high command processing speed.
Solution Approach 2:
The system uses feedback from verification results and memory cell status to continuously optimize command issuing order. By monitoring which memory cells require additional verification cycles and adjusting subsequent write commands accordingly, the system achieves both high productivity and reduced writing time for nonvolatile memory operations.
Data Source
AI summary
Writing time is shortened even in a memory writing time for each access unit is not constant. A writing time prediction information holding unit holds writing time prediction information for predicting the writing time in a plurality of memory modules for each of a plurality of memory modules. A request selecting unit preferentially selects a write request of which longer writing time is predicted out of a plurality of write requests requiring writing in each of a plurality of memory modules on the basis of the writing time prediction information.