Memory Controller Write Prioritization via Dirty Cache Lines
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Solution Overview
Problem
In multi-core, multi-threaded data processing systems, the throughput of the processor-memory interface is limited due to data locality loss and inefficient scheduling of spatially sequential accesses, leading to performance reductions and unnecessary energy consumption, with the electrical integrity of buses becoming difficult to maintain at higher signaling rates.
Innovation Solution
The solution involves expanding the effective depth of the memory controller's write queuing resources by leveraging the storage capacity of a lower level cache memory, prioritizing write operations over read operations based on the number of dirty cachelines, and implementing a coordinated writeback policy to efficiently group write operations and increase page mode write opportunities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the physical write queue depth is increased to improve scheduling of memory accesses, then memory access scheduling is improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent introduces a cache memory as an intermediary layer between the processor and system memory. The cache's storage capacity is leveraged to provide virtual write queueing, allowing the memory controller to schedule memory accesses effectively without physically expanding the write queue. This mediator approach resolves the contradiction by using existing cache infrastructure to achieve deeper queuing capability.
Solution Approach 2:
The cache memory serves multiple functions: it acts as both a standard cache for data storage and as a virtual write queue for memory access scheduling. By making the cache multi-functional, the system gains enhanced scheduling capability without adding dedicated queueing hardware, thus avoiding increased device complexity.
2Speed
If IO frequencies are scaled up to improve system performance, then processing speed is improved, but electrical integrity of buses becomes difficult to maintain
Solution Approach 1:
The patent implements periodic writeback operations where dirty cache lines are written to system memory in scheduled bursts rather than continuously. This periodic action allows the memory bus to settle between transactions, maintaining electrical integrity at higher frequencies by introducing natural pause periods in the data flow.
Solution Approach 2:
The system performs preliminary scheduling of write operations in the virtual write queue before executing them on the memory bus. By pre-organizing write transactions and grouping them efficiently, the system reduces the number of bus transitions and maintains more predictable timing patterns, which helps preserve electrical integrity at higher frequencies.
3Reliability
If gaps are inserted in memory access streams to maintain timing parameters, then electrical integrity is maintained, but effective memory bandwidth is significantly degraded
Solution Approach 1:
The patent maintains continuous useful action by keeping the memory bus busy with scheduled write operations from the virtual write queue. Instead of inserting idle gaps, the system continuously drains the queue of pre-scheduled write transactions, ensuring the bus remains productive while still meeting timing requirements through careful scheduling.
Solution Approach 2:
The virtual write queue mechanism allows the system to self-regulate memory access patterns. The memory controller autonomously schedules and groups write operations to maintain timing compliance without external intervention or manual gap insertion, thereby maintaining both reliability and bandwidth efficiency.
4Productivity
If write operations are prioritized over read operations based on dirty cachelines, then memory bus utilization is increased, but read operation latency may increase
Solution Approach 1:
The patent implements dynamic priority adjustment where the memory controller continuously monitors the number of dirty cache lines and adjusts write operation priority accordingly. When dirty lines exceed a threshold, write priority increases to flush the cache; when below the threshold, read operations resume normal priority. This dynamic adjustment balances bus utilization with read latency requirements.
Solution Approach 2:
The system changes the priority parameter of memory operations based on the state of dirty cache lines. By dynamically modifying operation priorities rather than using fixed priorities, the system optimizes memory bus utilization during cache flush scenarios while minimizing impact on normal read operations.
Data Source
AI summary
A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.