Memory Controller Dynamic Write Protection Release

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Solution Overview

Problem

Memory systems face inefficiencies in utilizing memory units with set write protection modes, as these units are not effectively managed for program operations, leading to underutilization and potential data storage challenges.

Innovation Solution

A memory controller with a program history manager and memory unit manager that identifies and releases write protection on sub-units not used during a set period, allowing for efficient use of memory units by converting them for internal operations like garbage collection and data storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If write protection mode is set on memory sub-units to ensure data security, then reliability is improved, but memory unit utilization deteriorates

Engineering Contradiction:
Improvedata securityVSAvoidmemory unit utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic management of write protection mode by tracking program operation histories and automatically releasing write protection on sub-units that have not been programmed during a set period. This transforms the static write protection mechanism into a dynamic one that adapts based on actual usage patterns, thereby improving memory unit utilization while maintaining data security where needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The memory controller automatically monitors program histories and manages write protection status without external intervention. The system self-identifies sub-units eligible for write protection release based on their program operation history, enabling autonomous optimization of memory utilization while preserving security requirements.

Inventive Principle:
Principle #25Self-service

2Reliability

If write protection mode is maintained on all sub-units to prevent unauthorized writing, then reliability is improved, but memory system efficiency deteriorates

Engineering Contradiction:
Improvewrite protectionVSAvoidmemory system efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies write protection selectively to specific sub-units based on their individual program operation histories rather than uniformly across all memory sub-units. Sub-units that have not been programmed during a set period have write protection released, while other sub-units maintain protection status. This localized approach optimizes system efficiency without compromising overall reliability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system changes the write protection parameter dynamically based on program operation history and time conditions. By monitoring whether sub-units have been programmed during a set period, the system adjusts the write protection status accordingly, transforming memory system efficiency without sacrificing the protective function where required.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If write protection mode is set on memory sub-units to ensure data integrity, then reliability is improved, but available memory capacity deteriorates

Engineering Contradiction:
Improvedata integrityVSAvoidavailable memory capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The system performs preliminary monitoring of program operation histories to identify sub-units that are candidates for write protection release. By proactively tracking which sub-units have not been programmed during a set period, the system prepares to release write protection in advance, thereby increasing available memory capacity while maintaining data integrity protection where necessary.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11137917B2Memory controller, memory system having the memory controller, and operating method of the memory controller
Publication Date: 2021.10.05 SK HYNIX INC
  • US11137917B2 patent drawing
  • US11137917B2 patent drawing
  • US11137917B2 patent drawing

AI summary

A memory system includes a memory controller. The memory controller includes a program history manager for managing a program history of a first memory unit including a plurality of sub-units of which write protection mode is set; and a memory unit manager for selecting, based on the program history, at least one sub-unit on which a program operation is not performed during a set period among the plurality of sub-units, and releasing the write protection mode of the at least one selected sub-unit.