Memory Controller Write Request Processing via Barrier Segmentation

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Solution Overview

Problem

The existing write request processing methods for non-volatile memory (NVM) systems are inefficient due to the sequential processing of write requests separated by memory barriers, limiting concurrent write requests and thus reducing storage utilization and processing efficiency.

Innovation Solution

A method where write requests are grouped into sets based on memory barriers, allowing parallel processing of log write requests and other write requests across different unoccupied storage units, prioritizing log write requests behind memory barriers to maximize concurrent processing without violating transaction consistency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory barriers are used to separate write requests to ensure transaction consistency, then transaction consistency is improved, but write request processing efficiency deteriorates due to sequential processing requirements

Engineering Contradiction:
Improvetransaction consistencyVSAvoidwrite request processing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments write requests into different types (log write requests, commit write requests, data write requests) and processes them differently. By identifying and prioritizing log write requests that can be processed behind memory barriers, the system creates separate processing paths that maintain transaction consistency while enabling parallel execution of compatible requests.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic scheduling of write requests based on their type and position relative to memory barriers. The memory controller dynamically adjusts processing order, allowing log write requests behind barriers to be processed in parallel with other requests, while maintaining the required sequential ordering for commit and data write requests that affect transaction consistency.

Inventive Principle:
Principle #15Dynamics

2Reliability

If write requests are processed sequentially due to memory barrier constraints, then transaction linearizability is maintained, but storage unit utilization deteriorates

Engineering Contradiction:
Improvetransaction linearizabilityVSAvoidstorage unit utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the write request queue into segments based on memory barrier positions and request types. By identifying log write requests that can be safely processed in parallel behind barriers, the system creates multiple processing streams that utilize multiple storage units simultaneously while preserving the linearizability requirement for critical transaction requests.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses memory barrier identification as an intermediary mechanism to mediate between parallel processing goals and sequential consistency requirements. By detecting barrier positions and using them to guide scheduling decisions, the system enables parallel execution of non-conflicting requests while maintaining the ordering guarantees required for transaction linearizability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If log write requests behind memory barriers are processed with higher priority, then write request processing efficiency is improved, but processing complexity increases

Engineering Contradiction:
Improvewrite request processing efficiencyVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent performs preliminary identification and classification of write requests when they are queued, marking log write requests that can be processed behind memory barriers. This advance classification enables efficient parallel processing without requiring complex real-time analysis, as the scheduling decisions are based on pre-computed request types and barrier positions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces request type identification and barrier position detection as intermediary mechanisms that simplify the scheduling complexity. By using these intermediaries to translate the complex constraints of transaction consistency into simple scheduling rules, the system achieves high processing efficiency without requiring complex real-time arbitration logic.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3287900B1Write request processing method and memory controller
Publication Date: 2020.12.02 HUAWEI TECH CO LTD
  • EP3287900B1 patent drawingFigure 1~2
  • EP3287900B1 patent drawingFigure 3
  • EP3287900B1 patent drawingFigure 4

AI summary

A write request processing method and a memory controller are provided. The method includes: determining that a quantity of write requests in a to-be-scheduled first write request set is less than a quantity of unoccupied storage units in a memory, where a first memory barrier exists between a write request in the first write request set and another write request in a write request queue, and the write request in the first write request set is located before the first memory barrier (310); determining a second write request set, where a write request in the second write request set is a log write request, the write request in the second write request set is located behind the first memory barrier in the write request queue, and the sum of a quantity of write requests in the second write request set and the quantity of write requests in the first write request set is not greater than the quantity of unoccupied storage units in the memory (320); and sending the write request in the first write request set and the write request in the second write request set in parallel to different unoccupied storage units in the memory (330). The method improves processing efficiency of a write request.