Memory Controller Write Request Scheduling for Variable Latency
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Solution Overview
Problem
Conventional memory controllers struggle to efficiently manage write operations in storage devices that utilize nonvolatile memories with variable write times, as they cannot appropriately change the command issuance order to shorten writing time.
Innovation Solution
A memory controller with a selection unit that identifies the state of each memory module and prioritizes write requests based on memory state information, using write request holding units and data processing units to preprocess and manage write requests and data for parallel access across multiple memory modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory controllers issue commands in fixed order to memory modules, then command issuance is simple, but write time cannot be shortened due to variable write times in nonvolatile memories
Solution Approach 1:
The patent applies preliminary action by pre-processing write data and pre-issuing write requests to memory modules before the actual write operation completes. The controller pre-issues commands to multiple memory modules in parallel, and when verification fails, it can immediately re-issue commands without waiting for previous operations to complete, thereby shortening overall write time while managing complexity through structured data holding units and selection logic
Solution Approach 2:
The patent implements dynamics by making the command issuance order adaptive rather than fixed. The selection unit dynamically determines which memory module receives the next write request based on real-time verification results and busy states of各memory modules. This dynamic adjustment allows the controller to optimize write operations for nonvolatile memories with variable write times, improving productivity while the modular architecture manages the added complexity
2Reliability
If memory controllers wait for write verification to complete before issuing next command, then write accuracy is ensured, but write time increases due to variable verification times in nonvolatile memories
Solution Approach 1:
The patent applies continuity of useful action by maintaining continuous command issuance to memory modules even when some modules are undergoing verification. The controller issues write requests to multiple memory modules in parallel, and when a verification fails, it immediately re-issues the command to that module without waiting for other modules to complete their operations. This continuous operation ensures reliability through verification while minimizing idle time, thereby reducing overall write time
Solution Approach 2:
The patent implements feedback by using verification results to dynamically control command issuance. The selection unit receives feedback about which memory modules have failed verification and which are currently busy, then uses this feedback to determine the optimal next command to issue. This feedback mechanism ensures write accuracy by re-issuing commands to modules that failed verification while maintaining system efficiency through intelligent command scheduling
3Productivity
If multiple write requests are issued in parallel to multiple memory modules, then processing capacity increases, but managing variable write times across modules becomes complex
Solution Approach 1:
The patent applies segmentation by dividing the command management function into distinct components: write request holding units for each memory module, a selection unit for determining next commands, and verification result processing logic. This segmentation allows parallel processing of multiple write requests while managing complexity through modular, specialized components. Each segment handles specific aspects of parallel write management, making the overall system more manageable despite handling multiple concurrent operations
Solution Approach 2:
The patent implements universality through the selection unit, which serves multiple functions: determining which memory module receives the next write request, checking verification results, identifying busy states of modules, and deciding when to re-issue commands. This multi-functional component manages the complexity of parallel write operations with a single intelligent unit, maintaining processing capacity while reducing overall system complexity through functional consolidation
Data Source
AI summary
The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories.In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.