Memory Controller Dynamic Write Synchronization
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Solution Overview
Problem
In memory systems with multiple NAND flash channels, differences in write process progress can lead to inefficiencies and decreased writing speed due to slower channels limiting faster channels, and existing methods fail to effectively manage these differences to maintain optimal performance.
Innovation Solution
A memory system with a controller that dynamically adjusts write settings, such as write time upper limits and error bit counts, across channels to synchronize progress, and in some embodiments, uses NULL data writing or mode changes to balance channel performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple NAND flash channels operate in parallel to improve writing speed, then data writing speed is improved, but differences in write process progress between channels cause slower channels to bottleneck faster channels
Solution Approach 1:
The patent dynamically adjusts write settings (such as write time upper limits and error bit counts) for each channel based on real-time write progress monitoring. This allows the system to adaptively balance the write speeds of different channels, preventing slower channels from bottlenecking faster ones while maintaining parallel operation efficiency.
Solution Approach 2:
The patent changes operational parameters (write time limits, error bit counts, write modes) for individual channels based on their write progress status. By modifying these parameters dynamically, the system optimizes each channel's write speed to match the overall parallel write performance, resolving the bottleneck issue.
2Loss of time
If write settings are adjusted to balance channel progress, then write time discrepancies are reduced, but system complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the memory controller continuously monitors write progress across multiple channels and uses this information to dynamically adjust write settings. This closed-loop control balances channel performance while keeping the complexity manageable through automated decision-making based on progress metrics.
Solution Approach 2:
The system performs self-adjustment by automatically monitoring its own write progress and modifying its operational parameters without external intervention. The memory controller autonomously balances channel performance by detecting progress differences and applying appropriate parameter changes, reducing the need for complex external control mechanisms.
Data Source
AI summary
According to one embodiment, a memory system includes a first and second nonvolatile memory each including a plurality of memory cells; and a memory controller configured to perform, in parallel, a first set of write processes sequentially performed on the first nonvolatile memory, and a second set of write processes sequentially performed on the second nonvolatile memory. The memory controller is configured to change a setting of at least one unperformed write process among the first set and second set of write processes based on differences in progress between the first set and second set of write processes, the first set and second set of write processes being performed in parallel.