Memory Controller Write Response Throttling for Stable Storage QoS
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Solution Overview
Problem
Existing storage devices face challenges in maintaining optimal Quality of Service (QoS) due to instantaneous latency increases when command processing exceeds capacity, leading to reduced QoS, despite using throttling techniques that delay commands, which do not guarantee optimized latency.
Innovation Solution
A memory controller with a buffer memory and processor that determines a throttle trigger value based on active range and base latency, delaying write completion responses to manage command processing efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed throttling technique is used to delay commands, then QoS is maintained through command delay, but optimal latency cannot be guaranteed due to fixed processing function
Solution Approach 1:
The patent implements dynamic throttling by adjusting the delay time of write completion responses based on real-time conditions. The host interface determines delay time dynamically using throttle trigger values and base latency values that vary according to workload characteristics, replacing the fixed processing function with an adaptive mechanism that responds to changing system states
Solution Approach 2:
The patent changes the parameter of delay time from a fixed value to a dynamically determined value. The host interface calculates delay time based on throttle trigger values (determined by active range from mapping information) and base latency values (determined by write ratio), allowing the system to adapt throttling intensity to current workload conditions
2Stability of the object's composition
If throttling is applied to prevent QoS reduction, then command processing uniformity is maintained, but latency increases instantaneously
Solution Approach 1:
The system dynamically adjusts throttling intensity by determining delay time based on current workload characteristics (throttle trigger value from active range and base latency from write ratio). This allows the system to maintain QoS uniformity while minimizing latency increases by adapting the throttling strength to actual system conditions rather than applying a fixed delay
Solution Approach 2:
The host interface implements feedback-based throttling by continuously monitoring workload characteristics (write ratio, active range) and adjusting the delay time of write completion responses accordingly. This feedback mechanism allows the system to maintain stable QoS while responding to changing workload conditions, preventing excessive latency accumulation
Data Source
AI summary
A memory controller that includes a buffer memory configured to store user data and a write command corresponding to a write request received from a host, a processor configured to control a memory device to perform a write operation, and a host interface configured to determine an active range based on mapping information of the memory device, determine the throttle trigger value based on the active range, determine a base latency based on a write ratio of the write command to commands received from the host, and determine a delay time of a write completion response based on the throttle trigger value and the base latency, delay the write completion response according to the delay time, and transmit the delayed write completion response to the host.