Memory Controller Write Time Difference Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory systems, the reliability of data stored in NAND flash memory deteriorates over time due to write time differences across blocks, leading to increased fail bits during read operations, which existing technologies fail to address effectively.
Innovation Solution
A memory system with a memory controller that detects write time differences by reading data from the first written region in a block and executes refresh processing and retry operations based on block management flags and shift amounts to maintain data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is continuously written to NAND flash memory blocks, then storage capacity is utilized, but write time differences cause threshold voltage shifts and increased fail bits
Solution Approach 1:
The patent applies preliminary action by performing read operations on the first written region immediately after writing to detect threshold voltage shifts before they cause data failures. The memory controller proactively monitors write time differences and prepares refresh operations in advance, preventing fail bits from accumulating to critical levels.
Solution Approach 2:
The patent implements feedback mechanisms where the memory controller continuously monitors read results from the first written region, detects threshold voltage shifts caused by write time differences, and automatically triggers refresh operations. This closed-loop feedback system dynamically adjusts refresh timing based on actual wear conditions, improving data reliability while optimizing refresh frequency.
2Reliability
If refresh processing is performed frequently to mitigate write time differences, then data reliability is improved, but processing time and system overhead increase
Solution Approach 1:
The patent applies local quality by performing refresh operations selectively on only the first written region of each block, rather than refreshing entire blocks or uniformly refreshing all regions. This localized approach concentrates refresh resources on the specific area most susceptible to write time difference effects, improving reliability while minimizing unnecessary processing time and overhead.
Solution Approach 2:
The patent dynamically changes refresh timing parameters based on detected threshold voltage shift amounts. When shift amounts exceed thresholds, refresh operations are triggered immediately; when shifts are minimal, refresh operations are delayed or skipped. This adaptive parameter adjustment optimizes the balance between data reliability and processing time overhead.
3Reliability
If retry operations are executed with voltage shifts to correct fail bits, then data read success rate is improved, but processing time increases
Solution Approach 1:
The patent applies partial action by performing voltage shift retry operations only on reads that fail initial attempts, rather than applying retries to all read operations. The system selectively applies corrective voltage shifts based on detected failures, improving read success rate for problematic reads while avoiding unnecessary processing time overhead for successful reads.
Solution Approach 2:
The patent prepares multiple voltage shift profiles in advance corresponding to different threshold voltage shift scenarios. When a read fails, the controller can immediately apply pre-calculated voltage corrections without performing complex real-time calculations, reducing retry processing time while maintaining high read success rates.
Data Source
AI summary
According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks each including a plurality of cell units, each of the cell units including a plurality of memory cells; and a memory controller. The memory controller is configured to read second data from a second cell unit in a first block in response to first data being written in a first cell unit in the first block, and reserve refresh processing for the first block when the second data satisfies a condition.