Memory Controller Data Stream Verification via Smart Card Write Token

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Solution Overview

Problem

Conventional methods for combining flash memory and smart cards face issues with data stream identification and transmission, leading to confusion between command data and regular file data, and the inability to bypass cache memory, which compromises encryption and communication security.

Innovation Solution

A method involving a host system that generates and records a write token, embeds it in data streams, and uses this token to verify the response data stream from a memory storage apparatus with a smart card chip, ensuring accurate identification and transmission of data streams by comparing verification codes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If special commands are used to distinguish data transmitted to smart card and flash memory, then data transmission can be directed to the correct device, but hardware devices or driver programs are unable to support the special commands

Engineering Contradiction:
Improvedata transmission directionVSAvoidcommand support
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent changes the identification method from using special commands to using type information parameters embedded in the data stream. The memory controller identifies whether data is for smart card or flash memory by examining the type information parameter, which eliminates the need for unsupported special commands while maintaining proper data routing capability

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If type information of data stream is compared to determine whether data is of smart card command format, then data can be routed correctly, but regular file data is misinterpreted as smart card data stream

Engineering Contradiction:
Improvedata stream identificationVSAvoiddata interpretation accuracy
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a verification code as an intermediary element that mediates between the data stream and the identification process. The verification code is generated based on both the type information and the data content, providing an additional layer of verification that prevents misinterpretation of regular file data as smart card commands while maintaining accurate data stream identification

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If data stream transmission goes through cache memory, then data can be buffered and accessed efficiently, but response from smart card is substituted by cached data compromising encryption and communication security

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidencryption security
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the memory controller verifies whether received data is actually a response from the smart card by checking the verification code. This feedback loop ensures that even if cached data is present, the system can identify and accept only genuine smart card responses, maintaining encryption security while allowing cache memory to function for efficiency

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9043549B2Memory storage apparatus, memory controller, and method for transmitting and identifying data stream
Publication Date: 2015.05.26 PHISON ELECTRONICS
  • US9043549B2 patent drawing
  • US9043549B2 patent drawing
  • US9043549B2 patent drawing

AI summary

A memory storage apparatus, a memory controller and method for transmitting and identifying data streams are provided. The memory controller passes at least a portion of a data stream received from a host system to a smart card chip of the memory storage apparatus. Then, the host system accurately receives a response message from the smart card chip by executing a plurality of read commands. The memory controller is capable of adding a first verification code to a response data stream sent to the host system, and is capable of adding a write token to each of data segments of the response data stream. The host system confirms the accuracy of the response data stream by verifying the first verification code or by verifying the write token of each of the data segments.