Memory Controller Data Recovery via XOR Computation
Solution Overview
Problem
Current flash memory devices face limitations in performance due to capacity constraints and reliability issues in high-speed buffer memories, which hinder the development of advanced large-capacity storage solutions.
Innovation Solution
A memory controller and storage device design that incorporates a DMA master device, program buffer memory, exclusive OR computing circuit, and buffer slave device with recovery buffer memory to ensure data integrity and completion, using a bus connection for data management and recovery in case of programming failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed buffer memory is used to supplement input and output speeds, then input and output performance is improved, but capacity limit and reliability guarantee deteriorate
Solution Approach 1:
The buffer memory is segmented into multiple independent buffer regions (first buffer region, second buffer region, third buffer region, fourth buffer region) with different functions. This segmentation allows the system to use high-speed buffer memory for data transfer while maintaining reliability through separate verification and recovery regions, resolving the contradiction between speed improvement and reliability guarantee.
Solution Approach 2:
The system performs preliminary verification by storing verification data in advance in the fourth buffer region before actual data transfer. This preliminary action enables the system to detect and recover from potential errors before they affect data integrity, allowing high-speed buffer memory to be used without compromising reliability.
2Speed
If high-speed buffer memory is used to supplement input and output speeds, then input and output performance is improved, but capacity limit deteriorates
Solution Approach 1:
The buffer memory capacity is divided into multiple functional segments (first through fourth buffer regions) with different sizes and purposes. This segmentation allows the system to optimize each region for specific functions, enabling high-speed data transfer in the first buffer region while using smaller verification and recovery regions, thus improving speed without requiring excessive total capacity.
Solution Approach 2:
The system uses partial verification and recovery mechanisms rather than complete redundancy. By implementing verification data storage and recovery functionality only where necessary (in the fourth buffer region), the system achieves reliability improvement without duplicating the entire buffer memory capacity, thus resolving the capacity limitation while maintaining high-speed performance.
3Reliability
If buffer slave device is connected to DMA master device through bus, then data recovery capability is improved, but device complexity increases
Solution Approach 1:
The buffer slave device combines multiple functions (verification data storage, recovery data generation, and recovery data storage) into a single integrated component connected through the existing bus. This merging approach improves data recovery capability without adding separate complex subsystems, as the buffer slave device leverages the existing bus infrastructure already present in the system.
Solution Approach 2:
The buffer slave device is designed with multi-functionality, serving both as a verification buffer and a recovery mechanism. By making the buffer slave device universal in its functionality, the system achieves improved data recovery capability without adding dedicated separate components, thus minimizing the increase in device complexity while enhancing reliability.
Data Source
AI summary
A memory controller comprising a DMA master device configured to provide a first data group to a non-volatile memory (NVM) device, a program buffer memory configured to temporarily store the first data group before the DMA master device provides the first data group to the NVM device, an exclusive OR computing circuit configured to perform an exclusive OR computation and an accumulation on a plurality of data included in the first data group provided from the program buffer memory to generate a first recovery data, after the DMA master device provides the first data group to the NVM device, and a buffer slave device including a first program recovery buffer memory configured to store the first recovery data and provide the first recovery data from the first program recovery buffer memory to the program buffer memory, in response to a program failure signal, may be provided.