Memory Controller Zero-Tracking Tables for Lower DRAM Access Overhead
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Solution Overview
Problem
Existing microprocessors face inefficiencies in memory access times due to the high cost of writing and reading zero-valued data to dynamic random access memory (DRAM), which consumes power and increases latency, and current methods to mitigate this are either costly or impractical.
Innovation Solution
Implementing a cache line zero tracking controller with two tables of varying granularity - a 4 KB table for tracking individual memory pages and a 2 MB table for tracking groups of pages - to efficiently manage zero-valued cache lines, reducing the need for DRAM access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If zero-valued data is written to DRAM, then data storage is achieved, but power consumption and access latency increase
Solution Approach 1:
The patent extracts the tracking of zero-valued cache lines from the general memory management system and implements it in a dedicated controller component. This separation allows the system to identify and handle zero-valued writes specially, avoiding unnecessary DRAM access for zero writes by tracking them in a separate manner through metadata bits in the cache line tags.
Solution Approach 2:
The patent introduces an intermediary tracking mechanism between the cache and DRAM. The controller uses metadata bits in cache line tags to intermediate the zero-write detection, preventing direct DRAM access for zero-valued writes while maintaining data integrity. This intermediary layer filters out unnecessary DRAM operations.
2Reliability
If zero-valued data is written to DRAM, then data storage is achieved, but memory access bandwidth is consumed
Solution Approach 1:
The patent extracts the tracking of zero-valued cache lines from the general memory management system and implements it in a dedicated controller component. This separation allows the system to identify and handle zero-valued writes specially, avoiding unnecessary DRAM access for zero writes by tracking them in a separate manner through metadata bits in the cache line tags.
Solution Approach 2:
The patent introduces an intermediary tracking mechanism between the cache and DRAM. The controller uses metadata bits in cache line tags to intermediate the zero-write detection, preventing direct DRAM access for zero-valued writes while maintaining data integrity. This intermediary layer filters out unnecessary DRAM operations.
3Device complexity
If a single table tracks all zero-valued cache lines, then tracking is simplified, but memory and power are wasted
Solution Approach 1:
The patent segments the tracking structure into multiple tables organized by set indices rather than using a single large table. Each table tracks zero-valued cache lines for a specific subset of sets, allowing the system to activate only the necessary tables based on the current access pattern. This segmentation reduces the active memory footprint and power consumption while maintaining tracking capability.
Solution Approach 2:
The patent implements a dynamic tracking structure where tables can be selectively activated and deactivated based on usage patterns. The controller dynamically manages which tracking tables are active, adjusting the tracking overhead to match actual workload requirements. This dynamic behavior optimizes power consumption by keeping only necessary tracking structures active.
4Reliability
If DRAM refresh is performed on zero-valued cells, then memory reliability is maintained, but power is wasted
Solution Approach 1:
The patent extracts the tracking of zero-valued cache lines from the general memory management system and implements it in a dedicated controller component. This separation allows the system to identify and handle zero-valued writes specially, avoiding unnecessary DRAM access for zero writes by tracking them in a separate manner through metadata bits in the cache line tags.
Solution Approach 2:
The patent introduces an intermediary tracking mechanism between the cache and DRAM. The controller uses metadata bits in cache line tags to intermediate the zero-write detection, preventing direct DRAM access for zero-valued writes while maintaining data integrity. This intermediary layer filters out unnecessary DRAM operations.
Data Source
AI summary
In one embodiment, a controller in a microprocessor, the controller configured to manage accesses to dynamic random access memory (DRAM), the controller comprising: a first table configured to track cache lines that have been written to zero for a plurality of first memory regions; and a second table configured to track the cache lines that have been written to zero for a plurality of second memory regions, wherein each of the plurality of second memory regions comprises a group of the plurality of first memory regions where all of the cache lines within each of the plurality of the first memory regions within the group have been written to zero.