In-Memory Convolution Circuit Using Global Bit-Line Multiplication
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Solution Overview
Problem
Conventional computer systems face challenges in efficiently performing complex machine learning operations like multiply-and-accumulate operations, leading to high power consumption and poor performance due to the lack of optimization for these tasks.
Innovation Solution
Implementing compute-memory circuits that utilize standard data storage cells and perform computations on global bit lines, eliminating the need for specialized cells, thereby enhancing area efficiency and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional computer systems are used to perform machine learning operations, then general-purpose computing capability is maintained, but power consumption increases and performance deteriorates
Solution Approach 1:
The patent merges memory storage and computation functions into a single integrated structure. Memory cells store weight values while simultaneously performing multiplication operations with input signals, eliminating the need for separate compute units and reducing data movement between memory and processor, thereby lowering power consumption while improving performance.
Solution Approach 2:
The patent introduces sense amplifiers as intermediary components that facilitate the interaction between memory cells and computation operations. These amplifiers read voltage levels from memory cells, interpret them as digital values, and enable multiplication operations, serving as a bridge between storage and computation functions.
2Productivity
If specialized data storage cells are used for in-memory computing, then computation capability is improved, but area efficiency decreases
Solution Approach 1:
The patent designs memory cells to serve multiple functions: storing weight values, performing multiplication operations, and providing digital outputs. This multi-functionality allows standard memory cell architectures to be used for both storage and computation, avoiding the need for specialized cells that would consume additional area while maintaining computation capability.
Solution Approach 2:
The patent uses homogeneous memory cell structures throughout the array, where each cell is identical and capable of performing the same storage and computation functions. This uniformity simplifies the overall architecture and improves area efficiency compared to heterogeneous designs that would require different specialized cell types for different functions.
Data Source
AI summary
A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of the global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit.