Memory Core Circuit Cell On Periphery Structure
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Solution Overview
Problem
Conventional DRAM devices face challenges in reducing size due to limitations in circuit arrangement for memory cell arrays, particularly with the implementation of vertical channel transistors, which restricts the miniaturization and integration of memory devices.
Innovation Solution
A memory core circuit with a cell on periphery (CoP) structure is implemented, where a core control circuit is disposed under a memory cell array, featuring a matrix arrangement of sub-cell arrays and sub-peripheral circuits with bitline sense amplifiers distributed to reduce wiring complexity and enhance integration, allowing for efficient placement of bitlines and wordlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional open bitline structure with bitline sense amplifiers spread on both sides is used, then sensing function is achieved, but device size reduction is limited due to wiring complexity and circuit arrangement limitations
Solution Approach 1:
The memory device is divided into multiple cell blocks, with each block containing sub-cell arrays and associated peripheral circuits. This segmentation allows independent optimization of each block's layout, reducing overall wiring complexity while enabling size reduction through efficient packing of segmented units
Solution Approach 2:
The patent transitions from a planar arrangement where sense amplifiers are spread on both sides of bitlines to a vertical stacking approach where sense amplifiers are positioned above or below cell blocks in the third dimension. This dimensional change reduces planar wiring complexity while maintaining sensing functionality
2Volume of moving object
If vertical channel transistor is implemented to reduce memory device size, then integration density improves, but circuit arrangement for driving memory cell array becomes more difficult
Solution Approach 1:
Each cell block is further divided into multiple sub-cell arrays, with dedicated peripheral circuits for each sub-cell array. This fine-grained segmentation simplifies the circuit arrangement by localizing control functions, making it easier to integrate vertical channel transistors while maintaining manufacturability
Solution Approach 2:
Peripheral circuits act as intermediary components between the vertical channel transistors in sub-cell arrays and the external control signals. These intermediary circuits buffer and condition signals, simplifying the overall circuit arrangement and making the system easier to manufacture despite using advanced vertical transistor structures
Data Source
AI summary
A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit, which includes sub peripheral circuits that are disposed under each sub cell array. Each sub peripheral circuit includes a sense amplifier region, which includes a plurality of bitline sense amplifiers, and a rest circuit region, which includes other circuits. First-type bitline sense amplifiers, which are connected to first-type bitlines, are disposed in the sense amplifier region of each sub peripheral circuit, and the first-type bitlines are disposed above the sense amplifier region of each sub peripheral circuit. Second-type bitline sense amplifiers, which are connected to second-type bitlines, are disposed in the sense amplifier region of a neighboring sub peripheral circuit adjacent in the column direction to a first sub peripheral circuit of the sub peripheral circuit, and the second-type bitlines are disposed above the rest region of each sub peripheral circuit.