Semiconductor Memory Global Core Line Controller Segmentation
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Solution Overview
Problem
As memory density increases from 512 MB to 1 GB and the multi-bank structure changes from an 8-bank to a 16-bank structure, conventional semiconductor memory devices face issues with increased loading and junction of global lines, leading to timing delays and voltage level slopes, which hinder normal operation and expand layout area.
Innovation Solution
The semiconductor memory device addresses this by dividing bank regions for read and write operations and generating bank strobe signals within the bank region instead of the peripheral region, using a global core line controller to separately manage left and right banks through dedicated global core lines, reducing the loading and junction of global lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the multi-bank structure changes from an 8-bank to a 16-bank structure to increase memory density, then the memory capacity is improved, but the loading and junction of global lines increase causing timing delays and voltage level slopes
Solution Approach 1:
The patent divides the 16 banks into four groups of four banks each, with each group having dedicated global core lines. This segmentation reduces the loading on individual global lines by distributing the data transfer load across multiple dedicated lines, thereby reducing timing delays and voltage level slopes while maintaining 16-bank capacity.
Solution Approach 2:
The patent introduces a new organizational dimension by grouping banks into quarters (QA, QB, QC, QD) with dedicated global core lines for each quarter. This dimensional reorganization allows independent data transfer paths for different bank groups, reducing the junction load on global lines and improving signal integrity.
2Quantity of substance
If the number of banks increases from 8 to 16 to improve memory density, then the memory capacity is improved, but the layout area expands due to increased global line junctions
Solution Approach 1:
The patent segments the 16 banks into four quarter-groups, each with dedicated global core lines. This segmentation allows for a more compact layout by reducing the number of global line junctions required, as each quarter-group has its own dedicated lines rather than all banks sharing common global lines.
Solution Approach 2:
The patent merges banks into quarter-groups (QA, QB, QC, QD) that share dedicated global core lines. This combining approach reduces the overall layout area by consolidating the routing paths for multiple banks into dedicated channels, avoiding the need for extensive global line junctions that would be required if all 16 banks were independently connected.
3Device complexity
If bank strobe signals are generated in the peripheral region as in conventional designs, then the control structure is simplified, but the loading and junction of global lines increase
Solution Approach 1:
Instead of generating bank strobe signals in the peripheral region and distributing them through global lines, the patent inverts the approach by generating bank strobe signals locally within each quarter-group at the bank region. This inversion eliminates the need for long global line transmissions of control signals, reducing loading and improving signal integrity.
Solution Approach 2:
The patent introduces quarter-group level control logic as an intermediary between the peripheral control and the banks. Each quarter-group has its own control logic that generates bank strobe signals locally, acting as an intermediary that reduces the burden on global lines by handling control signal generation at a closer, more localized level.
Data Source
AI summary
A semiconductor memory device includes: a global input/output line; a first global core line; a second global core line; a global core line controller disposed between the first global core line and the second global core line; a first bank coupled to the global core line controller through the first global core line; and a second bank coupled to the global core line controller through the second global core line.