Memory Core Metadata Routing by Column-Selected Meta Storage

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing memory devices face inefficiencies in managing and processing metadata, particularly in operations involving multiple memory cores and storage circuits, leading to suboptimal data and metadata handling.

Innovation Solution

A memory device architecture that includes multiple memory cores and meta storage circuits, allowing for specific operations like meta write, read, internal meta write, and read, and parallel-write operations, with metadata handling based on column addresses, enhancing data and metadata management efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple memory cores and meta storage circuits are introduced to enhance data management capability, then the productivity and operational flexibility are improved, but the device complexity increases

Engineering Contradiction:

Improvedata and metadata handling efficiencyVSAvoidmemory device structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The memory device is divided into multiple memory cores (first memory core, second memory core, etc.) each with dedicated meta storage circuits. This segmentation allows independent operation and management of data and metadata for different memory cores, improving overall productivity while keeping each individual core's structure relatively simple and manageable.

Inventive Principle:

Principle #1Segmentation

2Reliability

If separate meta storage circuits are assigned to each memory core, then the reliability of metadata management is improved, but the device complexity increases

Engineering Contradiction:

Improvemetadata management reliabilityVSAvoidstorage circuit configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Each memory core is assigned its own dedicated meta storage circuit, creating isolated metadata management paths. This prevents metadata conflicts between cores and ensures reliable metadata management for each core independently, while the modular nature of separate circuits makes the complexity manageable through standardization.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The meta storage circuits are designed to serve multiple functions including storing metadata, performing internal meta read/write operations, and supporting parallel operations. This multi-functionality improves reliability by consolidating management tasks while the universal design pattern helps manage complexity through reuse of circuit configurations.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If internal meta read/write operations are implemented to enable metadata exchange between memory cores, then the adaptability and operational flexibility are improved, but the device complexity increases

Engineering Contradiction:

Improvemetadata operation flexibilityVSAvoidinternal operation control

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Meta storage circuits act as intermediaries between memory cores, enabling metadata exchange through standardized internal read/write operations. This intermediary layer simplifies the complexity of direct core-to-core communication by providing a uniform interface for metadata management across different cores.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The internal meta read/write operations provide a universal mechanism that works across all memory cores for metadata exchange. This standardized approach improves adaptability by allowing flexible metadata operations between any cores while managing complexity through a single operational paradigm rather than core-specific protocols.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Productivity

If parallel-write operations with test voltage storage are added to enhance testing capability, then the productivity of quality verification is improved, but the device complexity increases

Engineering Contradiction:

Improvequality verification speedVSAvoidtesting operation structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Test voltage is stored in meta storage circuits during normal operation or setup phases, preparing the testing infrastructure in advance. This preliminary action enables rapid quality verification when needed without requiring complex real-time testing infrastructure, thus improving productivity while managing complexity through advance preparation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The meta storage circuits serve dual purposes: normal metadata storage operations and test voltage storage for quality verification. This multi-functionality improves productivity by reusing existing infrastructure for testing rather than adding separate dedicated test equipment, while the universal design helps manage complexity through a single circuit type performing multiple functions.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250356936A1Method of processing metadata and memory device performing the method

Publication Date: 2025.11.20 SK HYNIX INC

AI summary

A memory device include a plurality of memory cores and a plurality of meta storage circuits, each of the plurality of meta storage circuits corresponding to a different one of the plurality of memory cores. In an embodiment, when a meta write operation is performed, data that are received through an external line are stored in the plurality of memory cores based on a column address, and metadata that are received through a meta line are stored in a meta storage circuit, among the plurality of meta storage circuits, that is selected by the column address.