Memory Core ECC Architecture with On-Device Parity Correction
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Solution Overview
Problem
Conventional semiconductor memory devices face increased error probability due to reduced cell size, as error correction operations are typically performed only at the memory controller level, failing to effectively correct errors in individual devices connected through a memory channel.
Innovation Solution
A semiconductor device with a memory core containing data and parity cell regions, along with error correcting logic and parity calculation logic, allows for internal command and address generation to perform error correction operations, enabling individual devices to correct errors and reducing overall error probability by secondary correction from the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction operation is performed only at memory controller level, then device complexity is reduced, but reliability deteriorates due to increased error probability from reduced cell size
Solution Approach 1:
The error correction function is segmented between individual semiconductor devices (primary correction) and the memory controller (secondary correction). Each device includes its own error correcting logic and parity cells for local error correction, while the memory controller provides additional correction capability for multiple devices connected through a memory channel. This segmentation allows error correction to be distributed, improving reliability without requiring all correction functionality to be concentrated in a single complex location.
2Productivity
If cell size is reduced to increase storage density, then productivity is improved, but reliability deteriorates due to increased error occurrence probability
Solution Approach 1:
Parity cells are pre-configured alongside data cells during manufacturing, creating a built-in error correction mechanism before errors occur. The parity calculation logic continuously maintains parity information that can be used for error detection and correction. This preliminary preparation of correction resources allows the system to handle errors that inevitably arise from reduced cell size, maintaining reliability while achieving high storage density.
Data Source
AI summary
A semiconductor device may include a memory core including a data cell region and a parity cell region, a parity calculation logic configured for generating a parity from data received by the parity calculation logic, and an error correcting logic configured for outputting error-corrected data by using data that is output from the data cell region and a parity that is output from the parity cell region.