Memory Core Power-Up Sequencing via Control Transistor Threshold
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Solution Overview
Problem
Existing memory technologies face challenges with high peak current during power-up, which can damage the memory and require lengthy power-up times due to fixed RC delays that are sensitive to process, voltage, and temperature variations, making design porting across different process nodes difficult.
Innovation Solution
The solution involves segregating the power supply to bitcells by input/output (IO) and using a control transistor to sequentially power up memory cores, where each core's power supply rail charges from ground to the core power supply voltage, with the charging of one core controlling the start of the next core's charging, eliminating the need for rigid fixed delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all power switch transistors are switched on simultaneously at power-up, then all bitcells are powered up at the same time, but this results in significant peak input current that can damage the memory
Solution Approach 1:
The patent segments the power-up process by dividing memory banks into groups and powering them up sequentially rather than simultaneously. Each group of memory banks is powered up in a staged manner, with control logic enabling subsequent groups only after previous groups are fully powered. This segmentation reduces the peak current draw while maintaining acceptable power-up speed.
2Object-affected harmful factors
If memory banks are sequenced by memory banks to reduce peak current, then peak input current is reduced, but the power-up time becomes lengthy due to fixed RC delays
Solution Approach 1:
The patent employs dynamic delay adjustment where the delay between powering up different groups of memory banks is not fixed but adapts based on detection signals. The control logic monitors the power-up status of each group and adjusts the timing dynamically, allowing shorter delays when conditions permit and longer delays when needed, thus reducing overall power-up time while still limiting peak current.
3Reliability
If fixed RC delay is used for sequencing memory banks, then power-up sequencing is controlled, but the delay must be changed when memory bank size is changed, making design porting problematic
Solution Approach 1:
The control logic in the patent is designed to automatically detect the configuration of memory banks and adjust its sequencing behavior accordingly. Rather than requiring external configuration or fixed delays that must be manually changed, the system self-adapts to different memory bank sizes and arrangements by detecting the presence and status of memory banks, enabling seamless design porting across different configurations.
4Reliability
If all process corners are satisfied with fixed delay, then reliability is ensured, but the resulting power-up time is lengthy
Solution Approach 1:
The patent incorporates feedback mechanisms where control logic monitors the actual power-up status of memory banks and uses this information to adjust subsequent sequencing decisions. Detection signals from each memory bank group provide real-time feedback to the control logic, allowing the system to optimize the power-up sequence dynamically. This ensures all process corners are satisfied while minimizing power-up time by avoiding unnecessary delays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces peak input current during memory power-up without excessive delay, allowing for more efficient and flexible power-up sequences across varying conditions and memory bank sizes.
Implementation Method 1
a control transistor having a gate connected to the first core power supply rail, wherein the second power switch transistor is configured to switch on in response to a switch on of the control transistor
Data Source
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AI summary
A memory is provided with a plurality of cores that power up according to a power-up order from a first core to a final core. As the core power supply voltage for a current core powers up according to the power-up order, it triggers the power-up of a succeeding core in the power-up order responsive to the core power supply voltage exceeding the threshold voltage of a control transistor in the succeeding core.