Memory Core Power-Up Sequencing for Reduced Peak Current
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Solution Overview
Problem
Existing memory technologies face challenges with high peak current during power-up, which can damage the memory and require lengthy power-up times due to fixed RC delays that are sensitive to process, voltage, and temperature variations, making design porting across different process nodes difficult.
Innovation Solution
The memory architecture segregates power supply to bitcells by input/output, using multiple core power supply rails and control transistors to successively power up cores, where each core's power supply voltage controls the next core's power-up, eliminating the need for rigid fixed delays and allowing dynamic charging based on the ramping up of core power supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all power switch transistors are switched on simultaneously at power-up, then all bitcells are powered up at the same time, but this results in a significant peak input current that can damage the memory
Solution Approach 1:
The memory core is divided into multiple segments (first core and second core), each with its own power supply rail and power switch transistor. The power-up process is segmented into sequential phases where the first core is powered up before the second core, distributing the current demand over time and reducing the peak input current.
Solution Approach 2:
The first power switch transistor is switched on before the second power switch transistor, allowing the first core to be preliminarily powered up and stabilized before the second core begins its power-up sequence. This preliminary action ensures that the power-up process is controlled and peak current is reduced.
2Reliability
If fixed RC delay is used to sequence power-up of memory banks, then power-up sequencing is achieved, but the power-up time becomes lengthy to satisfy all process corners
Solution Approach 1:
The delay mechanism is changed from a fixed RC delay to a dynamic control scheme using control transistors. The control transistors dynamically control the switching timing of power switch transistors based on real-time conditions, allowing the power-up time to be optimized rather than constrained by fixed delays that must satisfy all process corners.
Solution Approach 2:
The control transistors are configured such that the gate of each control transistor is connected to the power supply rail of the preceding core. This self-service configuration allows the power-up process of one core to automatically trigger the power-up of the next core, eliminating the need for external delay logic and reducing overall power-up time.
3Reliability
If fixed RC delay is used for power-up sequencing, then sequencing is achieved, but the delay must be changed when memory bank size is changed, making design porting problematic
Solution Approach 1:
The control transistor configuration provides a universal power-up sequencing mechanism that works across different memory bank sizes and process nodes. The self-service configuration where control transistor gates are connected to preceding core power supply rails creates a scalable architecture that maintains proper sequencing regardless of the number of cores or banks, eliminating the need to redesign delay logic for different configurations.
Data Source
AI summary
A memory is provided with a plurality of cores that power up according to a power-up order from a first core to a final core. As the core power supply voltage for a current core powers up according to the power-up order, it triggers the power-up of a succeeding core in the power-up order responsive to the core power supply voltage exceeding the threshold voltage of a control transistor in the succeeding core.