Memory Core Preprocessing for Lower-Latency Storage Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices and storage devices face challenges in reducing latency due to the lack of efficient preprocessing tasks before main operations, leading to suboptimal performance.
Innovation Solution
Implementing a memory device with a main core and subcores, controlled by a controller, that performs preprocessing tasks using preprocessing commands, followed by operation commands, and manages subcore states with a semaphore manager to optimize task execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If preprocessing tasks are performed sequentially before main operations, then task execution completeness is improved, but operation latency increases
Solution Approach 1:
The patent implements preprocessing tasks (such as voltage generation, bit line setup, and page buffer configuration) before the main memory operation is initiated. The controller identifies and executes these preprocessing tasks in advance, allowing the main operation to start sooner without compromising task completeness.
Solution Approach 2:
The patent divides the memory operation into distinct segments: preprocessing tasks and main operation tasks. Each segment is managed separately with dedicated task queues and execution flows, allowing preprocessing to occur independently and in parallel with other operations, thereby reducing overall latency while ensuring all necessary tasks are completed.
2Productivity
If multiple subcores are used for parallel processing, then operation performance is improved, but device complexity increases
Solution Approach 1:
The patent divides the processing unit into multiple independent subcores (first subcore, second subcore, etc.), each capable of executing tasks independently. This segmentation enables parallel processing of different task queues simultaneously, improving overall operation performance while maintaining manageable complexity through modular design.
Solution Approach 2:
Each subcore is designed with universal functionality to handle different types of tasks (preprocessing and main operations) through a common task execution mechanism. The subcores can be dynamically assigned different task types based on system needs, providing multi-functionality without requiring separate specialized hardware for each task type.
3Reliability
If subcores are locked to ensure task completion, then task reliability is improved, but processing speed decreases
Solution Approach 1:
The patent implements a dynamic locking mechanism where subcores are locked only when necessary to ensure task completion (such as during critical preprocessing operations), and unlocked promptly when tasks are completed or can proceed independently. This dynamic approach maintains reliability for critical tasks while minimizing locking overhead that would reduce processing speed.
Solution Approach 2:
The locking mechanism is activated in advance before critical tasks begin and is released as soon as the task completes or reaches a safe intermediate state. This preliminary action ensures that tasks have the necessary exclusivity to complete reliably, while the brief duration of locking minimizes the impact on overall processing speed.
Data Source
AI summary
A memory device may include a plurality of subcores and a main core configured to control a subcore of the plurality of subcores to perform a preprocessing task of a memory operation in response to a preprocessing command.