Semiconductor Memory Core Voltage Generation Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in generating a stable core voltage regardless of external power supply voltage levels, leading to insufficient phase margin and gain margin, particularly in high-frequency operations.
Innovation Solution
A detection circuit is implemented to detect variations in the external power supply voltage, allowing the core voltage generation circuit to adjust its voltage level and secure sufficient phase and gain margins by selectively operating compensators based on the detected voltage level, ensuring a uniform core voltage output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional core voltage generation circuit with fixed amplifier configuration is used, then the circuit structure is simple, but the phase margin and gain margin are insufficient leading to unstable core voltage when external power supply voltage varies
Solution Approach 1:
The patent implements a dynamic voltage generation circuit that automatically adjusts its operation based on detected external power supply voltage levels. The circuit transitions between different operational states (first voltage generation mode and second voltage generation mode) depending on whether the external voltage is above or below a reference level, ensuring stable core voltage output across varying input conditions without requiring manual intervention or complex external control.
Solution Approach 2:
The patent changes key operational parameters of the voltage generation circuit based on the detected external power supply voltage level. When the external voltage exceeds the reference voltage, the circuit operates in a first mode with specific amplifier gain and voltage levels; when it falls below, the circuit switches to a second mode with adjusted parameters. This parameter adaptation ensures reliable core voltage generation despite input voltage variations.
2Adaptability or versatility
If the external power supply voltage varies, then the circuit can operate with different input conditions, but the core voltage becomes unstable with insufficient phase and gain margins
Solution Approach 1:
The patent employs a feedback mechanism where the voltage generation circuit continuously monitors the external power supply voltage level and automatically adjusts its operation accordingly. The circuit detects whether the external voltage is above or below a reference voltage and switches between operational modes to maintain stable core voltage output, creating a closed-loop control system that ensures reliability across varying input conditions.
Solution Approach 2:
The circuit dynamically adapts its operational characteristics based on real-time detection of external voltage levels. By transitioning between first and second voltage generation modes depending on input conditions, the circuit maintains adequate phase and gain margins across the full range of expected power supply variations, ensuring stable core voltage delivery to the memory device.
3Productivity
If a two-stage amplifier with resistor-type connection is used, then the closed loop gain approaches 2, but the circuit has at least two poles resulting in insufficient phase margin for high frequency operations
Solution Approach 1:
The patent implements dynamic control of the amplifier stages, switching between different operational configurations based on the external voltage level. In the first voltage generation mode, the circuit operates with a configuration optimized for high-frequency stability; in the second mode, it adjusts to maintain adequate phase margins. This dynamic adaptation resolves the contradiction between amplification efficiency and phase margin stability.
Data Source
AI summary
Semiconductor memory device includes a detection circuit configured to detect a voltage level of an external power supply voltage and a core voltage generation circuit configured to vary a voltage level of the core voltage according to an output signal of the detection circuit to generate a uniform core voltage.