Memory Error Correction via Dedicated Bus to Cut Row Switching
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Solution Overview
Problem
Conventional error correction systems in memory devices, such as DVD players, experience inefficiencies due to frequent change row operations when correcting errors, leading to excessive data access preparation time and reduced system efficiency, as they often need to switch between different memory rows during consecutive error correction operations.
Innovation Solution
An error correction device that directly accesses the main memory through a dedicated memory bus, allowing continuous data reading and writing without releasing bus control, thereby minimizing change row operations and optimizing system efficiency by using a separate memory bus and an interrupt condition to manage access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the error correction unit releases control of the system bus after reading error data to allow other function units to access the main memory, then other function units can utilize the system bus, but frequent change row operations occur when other function units access data in different rows, causing excessive data access preparation time
Solution Approach 1:
The patent divides the bus access rights by implementing a dedicated memory bus for the error correction unit, separating it from the system bus used by other function units. This segmentation allows the error correction unit to maintain continuous access to the main memory without releasing control to other units, thereby eliminating frequent change row operations and reducing data access preparation time while still allowing other units to operate independently on the system bus.
Solution Approach 2:
The patent introduces a dedicated memory bus as an intermediary channel between the error correction unit and the main memory. This separate bus allows the error correction unit to access memory continuously without interfering with or being interfered by other function units, thus avoiding the need to release bus control and preventing frequent change row operations that would consume preparation time.
2Productivity
If the error correction unit continuously accesses the main memory without releasing bus control, then change row operations are minimized and system efficiency is enhanced, but other function units may be interfered with during memory access
Solution Approach 1:
The patent segments the memory access path by providing a dedicated memory bus exclusively for the error correction unit, separate from the system bus used by other function units. This allows the error correction unit to continuously access the main memory without releasing control, minimizing change row operations and maximizing error correction speed, while other function units operate independently on the system bus without interference.
Solution Approach 2:
The patent adds a new dimension to the memory access architecture by introducing a separate memory bus channel. This dimensional separation allows the error correction unit to operate in its own access lane, maintaining continuous bus control for high-speed error correction while other function units operate simultaneously on the system bus, thus resolving the conflict between continuous access and bus sharing.
3Loss of time
If a dedicated memory bus is implemented for the error correction unit, then continuous data access is maintained and change row operations are reduced, but device complexity increases due to additional bus infrastructure
Solution Approach 1:
The patent implements a dedicated memory bus for the error correction unit, segmenting the memory access path from the main system bus. While this increases device complexity by adding bus infrastructure, it enables continuous memory access without releasing control, significantly reducing change row operations and memory access time. The segmentation isolates the error correction operations from system bus contention, providing a dedicated channel that eliminates access delays.
Data Source
AI summary
An error correction device includes a main memory, a memory bus coupled to the main memory, and a correction module. The correction module is coupled to the system bus and directly connected to the memory bus. The correction module reads an error data from the main memory via the memory bus according to an error address, generates a correct data according to the error data and an error value, and directly writes the correct data into the main memory via the memory bus. Because the correction module reads and writes the correct data into the main memory without using the system bus managed by an arbitrator, a number of the change row operations can be reduced to increase system efficiency.