Memory Device Count Circuit for Row Hammer Mitigation
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Solution Overview
Problem
The row hammering phenomenon occurs in memory devices due to increased coupling effects between adjacent word lines, leading to data damage in memory cells connected to frequently activated word lines before they can be refreshed.
Innovation Solution
A memory device is designed with a count circuit to generate group selection signals based on the frequency of address signal inputs, selecting a target group with the highest input frequency, and a sampling circuit to randomly sample a target address signal from this group for targeted refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of the memory device is increased, then the memory density is improved, but the coupling effect between adjacent word lines increases causing row hammering phenomenon
Solution Approach 1:
The patent performs preliminary actions by counting address signal inputs and identifying frequently accessed memory regions before the row hammering phenomenon can cause data damage. The count circuit monitors access patterns in advance, and the refresh operation is triggered proactively based on accumulated count values, preventing data deterioration before it occurs.
Solution Approach 2:
The patent implements feedback mechanisms where the count circuit continuously monitors address signal inputs and feeds back the count values to the refresh control logic. This feedback loop enables the system to adaptively identify frequently accessed regions and trigger targeted refresh operations based on real-time access patterns, effectively countering the coupling effect.
2Productivity
If a word line is frequently activated to improve data access speed, then the productivity is improved, but data in adjacent memory cells is damaged due to row hammering phenomenon
Solution Approach 1:
The count circuit provides continuous feedback on word line activation frequency, enabling the refresh control logic to identify and protect frequently accessed regions. This feedback mechanism allows the system to maintain high productivity through frequent access while simultaneously ensuring data integrity by triggering refresh operations based on accumulated activation counts.
Solution Approach 2:
The system performs preliminary refresh operations on frequently accessed memory regions before data damage occurs. By monitoring activation counts and triggering refresh proactively, the system maintains both high access speed and data integrity without requiring reduction in word line activation frequency.
3Reliability
If additional refresh operations are performed on adjacent word lines to prevent row hammering, then the reliability is improved, but the loss of time increases due to extra refresh cycles
Solution Approach 1:
The patent applies local quality by performing refresh operations only on frequently accessed memory regions identified through address counting, rather than uniformly refreshing all memory regions. This targeted approach maintains data protection reliability while minimizing time loss by concentrating refresh resources on vulnerable regions only.
Solution Approach 2:
The system performs partial refresh actions on specific frequently accessed regions rather than complete refresh of all memory. By applying refresh operations selectively based on count values, the system achieves sufficient data protection with reduced time overhead compared to comprehensive refresh strategies.
4Reliability
If a count circuit is added to track address signal frequency, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The count circuit is segmented into multiple independent count circuits, each associated with specific address groups. This segmentation allows parallel counting operations and simplifies the overall structure by dividing the monitoring function into manageable units, reducing the complexity burden while maintaining reliability.
Solution Approach 2:
The count circuit and refresh control logic serve multiple functions: they monitor address access patterns, identify frequently accessed regions, trigger targeted refresh operations, and adapt to different access patterns dynamically. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates the row hammering phenomenon by identifying and prioritizing memory regions with the highest access frequency for targeted refresh, thereby reducing data deterioration and enhancing memory device reliability.
Implementation Method 1
a count circuit suitable for: generating a plurality of group selection signals corresponding to a plurality of address groups by counting, in units of the address groups, a number of times that each of a plurality of address signals is inputted to the memory device
Implementation Method 2
a sampling circuit suitable for randomly sampling a target address signal from the target group based on the plurality of group selection signals and the plurality of address signals
Implementation Method 3
Each memory cell included in a memory device consists of a transistor that serves as a switch and a capacitor that stores charges (i.e., data). The memory device having such a structure performs a refresh operation to recharge data at predetermined periods in consideration of data loss due to leakage
Implementation Method 4
as a coupling effect between adjacent word lines increases, data in a memory cell connected to word lines adjacent to a frequently activated word line is damaged. When the Kth word line WLK toggles between an activated state and a deactivated state, voltages of the (K−1)th word line WLK−1 and the (K+1)th word line WLK+1 rise or fall due to a coupling phenomenon that occurs between the Kth word line WLK and the (K−1)th word line WLK−1 and a coupling phenomenon that occurs between the Kth word line WLK and the (K+1)th word line WLK+1
Data Source
AI summary
Disclosed is a memory device including a count circuit suitable for: generating a plurality of group selection signals corresponding to a plurality of address groups by counting, in units of the address groups, a number of times that each of a plurality of address signals is inputted to the memory device, wherein each of the address groups corresponds to one or more address signals from the plurality of address signals, and selecting a target group from the address groups, the target group corresponding to a greatest one of the numbers for the respective address groups, and a sampling circuit suitable for randomly sampling a target address signal from the target group based on the plurality of group selection signals and the plurality of address signals.