Memory Block Count Staggering for Sequential NAND Maintenance

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Solution Overview

Problem

The simultaneous checking of numerous memory blocks in rewritable non-volatile memory modules leads to significant delays and potential errors, potentially shortening the service life of the memory storage device.

Innovation Solution

Customizing the initial values of count information for physical management units in the memory storage device to ensure that maintenance operations are triggered sequentially, rather than simultaneously, by setting these values differently for each unit and updating them based on the reference number of operations performed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple memory blocks are checked simultaneously to ensure data correctness, then data reliability is improved, but operation time is increased and service life is shortened

Engineering Contradiction:
Improvedata correctnessVSAvoidchecking delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the memory blocks into multiple groups and assigns different initial count values to each group. This segmentation ensures that maintenance operations are triggered at different times for different groups, preventing simultaneous operations and reducing checking delays while maintaining data reliability through comprehensive maintenance coverage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent sets different initial count values for different memory block groups before actual maintenance operations occur. This preliminary action distributes the maintenance timing across different periods, ensuring that no single group undergoes maintenance all at once, thereby reducing operational delays and extending service life while still ensuring data correctness through systematic maintenance.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If count information is updated to reflect actual operation times, then accuracy of maintenance scheduling is improved, but complexity of management increases

Engineering Contradiction:
Improveoperation time recordingVSAvoidmanagement complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies different initial count values to different memory block groups based on their specific characteristics or usage patterns. This local quality approach allows precise tracking of operation times for each group while maintaining simple management through standardized update rules. The system records actual operation times accurately without requiring complex management mechanisms by using uniform update logic across all groups.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260050547A1Memory management method, memory storage device and memory control circuit unit
Publication Date: 2026.02.19 PHISON ELECTRONICS
  • US20260050547A1 patent drawing
  • US20260050547A1 patent drawing
  • US20260050547A1 patent drawing

AI summary

A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: setting an initial value of count information corresponding to at least one of a plurality of physical management units to be greater than zero; setting initial values of count information corresponding to at least two of the physical management units to be different from each other; and updating first count information corresponding to a first physical management unit among the physical management units according to a first operation performed on the first physical management unit, wherein the first count information reflects a reference number of times of performing the first operation on the first physical management unit, and the reference number of times is greater than an actual number of times of performing the first operation on the first physical management unit.