Memory Counter Validation via Parity and Multiplexing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory systems face challenges in efficiently testing and validating local counters used for row hammer mitigation, which can lead to increased latency and reduced memory cell density due to the use of access lines and limited testing capabilities.
Innovation Solution
Incorporating an error correction code (ECC) circuit and a bank of multiplexers to test counters tracking row activations, where the counter values are stored in memory cells, allowing for validation of counter correctness and incrementation during testing, and discarding faulty rows to maintain system integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If counters are implemented using access lines for row hammer mitigation, then row hammer protection is achieved, but latency increases and memory cell density decreases
Solution Approach 1:
The memory system is divided into multiple banks, with each bank having its own dedicated counter. This segmentation allows parallel operation of counters across different banks, reducing the overall latency for counter operations while maintaining comprehensive row hammer protection across the entire memory system.
Solution Approach 2:
A counter read port is introduced as an intermediary component that interfaces with the counters without requiring access lines. This mediator enables counter reading through a dedicated path, eliminating the latency penalty of using access lines for counter operations while preserving row hammer mitigation functionality.
2Reliability
If counters are implemented using access lines, then row hammer mitigation is enabled, but memory cell density is reduced
Solution Approach 1:
The counter read port serves multiple functions: it reads counter values for row hammer detection, validates counter correctness through parity checking, and supports testing operations. This multi-functionality eliminates the need for dedicated access lines for counter operations, preserving memory cell density while enabling comprehensive counter functionality.
Solution Approach 2:
The counter read port acts as an intermediary that provides a dedicated interface for counter operations, separating counter access from the main memory access lines. This isolation prevents counter infrastructure from consuming memory cell resources, maintaining high memory cell density while enabling row hammer mitigation.
3Difficulty of detecting and measuring
If counters are integrated into memory cells, then testing capability is improved, but counter correctness validation becomes more complex
Solution Approach 1:
Parity bits are generated based on counter values and fed back to the counter read port for validation. This feedback mechanism automatically verifies counter correctness by comparing the actual counter value against the expected parity, simplifying the validation process while enhancing testing capability without increasing overall system complexity.
Solution Approach 2:
The counter system includes self-validation capabilities through parity bits that are automatically generated and checked. The counter read port performs automatic parity verification, enabling the system to self-validate counter correctness without external intervention, thereby improving testing capability while keeping the validation process integrated and manageable.
Data Source
AI summary
Methods, systems, and devices for testing operations for memory systems are described. A memory system may include a first circuit and a second circuit configured to test one or more counters tracking the quantity of activates to respective rows of memory cells. In some examples, the memory system may initiate an operation to validate a counter of the memory system. The first circuit may determine if a value of the counter is correct by comparing a set of counter bits representing the value of the counter to a set of parity bits. Subsequently, the second circuit may determine if the counter is incrementing correctly in accordance with a set quantity of activates to the corresponding row of memory cells. If the first circuit or the second circuit detect an error associated with the counter, the memory system may discard the row of memory cells associated with the faulty counter.