Memory Block Counter Refresh for Stable 3D NAND Reads
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Solution Overview
Problem
3D NAND-type memory devices exhibit unstable read behavior due to shifts in voltage threshold of memory cells, leading to increased read errors, which traditional dummy read operations attempt to mitigate but at the cost of increased power consumption and potential QoS degradation.
Innovation Solution
Implementing counters to manage and refresh the transient state of memory blocks by performing dummy read operations selectively based on temperature and time intervals, optimizing the timing of these operations to reduce unnecessary power consumption and maintain device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional dummy read operations are performed to mitigate unstable read behavior, then read errors are reduced, but power consumption increases and QoS degrades
Solution Approach 1:
The patent changes the parameter of dummy read operation timing by using a counter to track time intervals since the last dummy read. The counter is compared against a threshold value to determine when to perform the next dummy read, transitioning from continuous or frequent dummy reads to conditional, time-based dummy reads, thereby reducing power consumption while maintaining read accuracy.
Solution Approach 2:
Instead of performing dummy read operations continuously or at every read cycle, the patent applies partial action by only performing dummy reads when the counter exceeds the threshold. This selective application of dummy reads provides sufficient mitigation of read errors without the excessive power consumption of continuous dummy reads.
2Reliability
If dummy read operations are performed frequently to maintain stable read behavior, then read errors are reduced, but QoS degrades
Solution Approach 1:
The patent implements periodic action by using a counter to track time intervals and performing dummy read operations only when the counter exceeds a threshold value. This creates a periodic, time-based schedule for dummy reads rather than continuous operations, maintaining read stability while improving QoS by reducing unnecessary operations that block normal read access.
3Reliability
If continuous monitoring and refreshing of memory block state is performed, then read accuracy is maintained, but power consumption increases
Solution Approach 1:
The system performs self-service by using a counter that automatically tracks the time interval since the last dummy read and compares it against a threshold. This self-monitoring mechanism eliminates the need for continuous external control or monitoring, maintaining read accuracy through automatic, threshold-based dummy read triggering while reducing power consumption by avoiding continuous active monitoring.
Data Source
AI summary
Various embodiments described herein provide for using one or more counters for refreshing a transient state of one or more memory blocks of a memory device (e.g., a NAND-type memory device, such as a 3D NAND-type memory device) of a memory system.