Non-Volatile Memory Counter Layout for Power-Loss-Safe Writes
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Solution Overview
Problem
Non-volatile memories, such as EEPROM, face limitations in write endurance and power loss during write operations, making simple counter storage unreliable and prone to errors, especially when spanning multiple bytes or pages.
Innovation Solution
Implementing a counter in non-volatile memory using two binary counters and two linear counters, where writes are minimized by determining which counter contains the current count, allowing linear counter writes in program-only mode to prevent data loss in case of power failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a counter is incrementally written to non-volatile memory without wear leveling, then the counter can be implemented in non-volatile memory, but the counter has an upper limit of 100K cycles due to write endurance limits
Solution Approach 1:
The counter is divided into multiple segments stored at different memory locations. Instead of incrementing a single counter location, the system segments the counter value across multiple memory locations, allowing wear to be distributed and individual segments to be refreshed or rewritten independently, thereby extending the overall counter lifecycle beyond the 100K cycle limit of individual memory cells.
Solution Approach 2:
The system recycles memory locations that have reached their write endurance limit. When a memory location can no longer be reliably written to, it is discarded from active use and recovered by redistributing the counter segments to different memory locations, effectively resetting the wear clock for those locations and enabling continued counter operation.
2Reliability
If power is lost during the erase/write cycle of EEPROM, then the memory location might be in an erased state or in a partially programmed state, but implementing a counter requires complete write operations
Solution Approach 1:
The system performs preliminary actions by implementing check and repair operations before finalizing counter writes. These preliminary checks detect partially programmed states or erased states that may result from power loss, and the repair operations restore the counter data to its correct state, ensuring data integrity without requiring complete rewrite of the entire counter.
Solution Approach 2:
The system uses feedback mechanisms to monitor the state of memory locations during and after write operations. By reading back the written data and comparing it with the expected counter value, the system can detect write failures or partial programming and trigger corrective actions, thereby maintaining counter integrity despite power loss during write cycles.
3Reliability
If check/repair operations are performed to ensure counter integrity, then data reliability is improved, but the operations are time consuming
Solution Approach 1:
Instead of performing exhaustive check and repair operations on the entire counter, the system applies partial checking focused only on critical segments or locations that are most susceptible to write errors. This selective approach maintains data integrity for the most vulnerable parts of the counter while minimizing the time spent on verification and repair operations.
Data Source
AI summary
A counter is efficiently implemented in non-volatile memory by using two binary counters and selectively using one or the other as a current counter. Writes to the binary counters are minimized by using two linear counters and using the state of the binary counters to determine which binary counter contains the current count. Write operations can be performed to the “not current” binary counter with the final write operation being to the linear counters. The linear counter write operations can be in program-only mode so that a power failure will not result in a loss of counts.