Memory Coupled Compiling for Reconfigurable Chips
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Solution Overview
Problem
Existing reconfigurable processor compilation methods face inefficiencies due to vague and incorrect usage of mapping and memory access, leading to prolonged compiling times and suboptimal performance.
Innovation Solution
A memory coupled compiling method and system that adjusts data flow graphs by acquiring a cycle number and using a heuristic algorithm to determine linear transformation vectors, ensuring the cycle number of the longest path remains unchanged or is increased, thereby optimizing memory mapping and reducing compiling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional LLVM compilation framework is used for reconfigurable processor, then high-level software programming languages can be compiled, but mapping and memory access are vaguely used leading to prolonged compiling times
Solution Approach 1:
The patent performs preliminary actions by pre-calculating and storing optimal mapping relationships and memory access patterns in lookup tables before compilation. The compiler queries these pre-prepared tables during compilation to quickly obtain mapping results and memory access information, avoiding complex real-time calculations and significantly reducing compilation time.
Solution Approach 2:
The patent introduces intermediate representation (IR) as a mediator between high-level programming languages and hardware implementation. The compilation process transforms source code into IR, then uses pre-prepared mapping tables to convert IR into hardware configuration, simplifying the complex mapping process and improving compilation efficiency.
2Ease of operation
If data flow graph adjustment is performed to optimize memory mapping, then memory access efficiency is improved, but compilation process becomes more complex
Solution Approach 1:
The patent optimizes memory access efficiency by adjusting parameters of the data flow graph, such as node positions, edge weights, and path lengths. By changing these parameters, the compiler can find optimal memory mapping solutions that improve access efficiency while keeping the adjustment process manageable through systematic parameter optimization.
Solution Approach 2:
The patent implements feedback mechanisms where the compiler evaluates memory access patterns after each data flow graph adjustment, compares the results with optimal targets, and uses this feedback to guide further adjustments. This iterative feedback process systematically improves memory access efficiency while avoiding arbitrary complex modifications.
3Measurement precision
If heuristic algorithm is used to acquire linear array of linear transformation vector, then memory mapping accuracy is improved, but if not acquired, data flow graph adjustment is required increasing compiling time
Solution Approach 1:
The patent uses heuristic algorithms to pre-calculate and identify optimal linear arrays of linear transformation vectors before the main compilation process. These pre-identified arrays are stored and directly applied during compilation, ensuring high memory mapping accuracy while avoiding time-consuming iterative adjustments during the actual compilation phase.
Data Source
AI summary
Provided are a memory coupled compiling method and system of a reconfigurable chip. The memory coupled compiling method includes: acquiring a cycle number of a data flow graph (DFG); acquiring a linear transformation vector of the cycle number through a mapping time difference; determining whether a linear array of the linear transformation vector is acquired by a heuristic algorithm; acquiring a memory mapping result through a current DFG or acquiring a cycle number of the current DFG until the linear array is acquired, depending on the determination result.