Nonvolatile Memory Coupling Plate Integration
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Solution Overview
Problem
The integration degree of embedded memory in System on Chip (SoC) devices is limited due to the difficulty in increasing the density of memory cells while maintaining productivity, as existing technologies require additional masks and complex processes for forming multiple gates in logic processes.
Innovation Solution
A nonvolatile memory device with a coupling plate in the device isolation layer that overlaps with the floating gate, allowing for improved integration and productivity by reducing the need for additional masks and enabling efficient coupling with the selection gate, thereby enhancing the integration degree and operating characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional masks and complex processes are used to form multiple gates in logic processes, then the integration degree of embedded memory is improved, but the productivity and fabrication complexity increase
Solution Approach 1:
The patent merges the formation of multiple gates (floating gate and selection gate) into a single fabrication process step. The gates are formed simultaneously using one mask pattern, eliminating the need for additional masks and process steps while achieving the required integration degree.
Solution Approach 2:
The single mask process serves multiple functions: it defines both the floating gate and selection gate patterns, performs alignment, and creates the necessary structural relationships between gates, thereby reducing overall fabrication complexity.
2Manufacturing precision
If additional masks and complex processes are used to form multiple gates in logic processes, then the integration degree of embedded memory is improved, but the productivity decreases
Solution Approach 1:
The patent combines multiple gate formation operations into a single process step, reducing the number of fabrication steps required. This directly improves productivity by decreasing cycle time and increasing throughput while maintaining the integration degree.
Solution Approach 2:
The single mask process performs preliminary patterning for both gates simultaneously, establishing their relative positions and structures in advance, which eliminates subsequent alignment and patterning steps that would reduce productivity.
3Manufacturing precision
If coupling plate is formed in device isolation layer overlapping with floating gate, then the integration degree is improved, but the device structure complexity increases
Solution Approach 1:
The coupling plate is nested within the device isolation layer, utilizing the existing isolation structure to house the coupling plate. This approach integrates the coupling function without adding external structural elements, thereby improving integration degree while minimizing structural complexity.
Solution Approach 2:
The device isolation layer serves as an intermediary structure that contains the coupling plate. This mediator approach allows the coupling plate to be integrated into the device without directly complicating the active device structure, as the isolation layer already provides the necessary structural framework.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases the integration degree of nonvolatile memory devices, improves operating characteristics, and maintains productivity by using a coupling plate in the device isolation layer to couple the floating gate, allowing for various programming and erasing methods without restricting bias polarity, thus reducing the size of peripheral circuits and simplifying the fabrication process.
Implementation Method 1
a coupling plate formed in the device isolation layer and overlapped with the floating gate
Data Source
AI summary
A nonvolatile memory device includes a substrate including a device isolation layer defining an active region, a floating gate and a selection gate arranged side by side at intervals of a first gap over the substrate, a coupling plate formed in the device isolation layer and overlapped with the floating gate, and a contact plug suitable for electrically coupling the coupling plate and the selection gate.