Nonvolatile Memory Bit Line Coupling Resistance Control
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Solution Overview
Problem
The increasing width of threshold voltage distribution in nonvolatile memory devices, particularly in Multi-Level Cell (MLC) type devices, leads to errors during read operations due to interference phenomena and under-programmed cells, making it difficult to set proper read voltage levels and secure read margins.
Innovation Solution
The method involves determining program operations for even and odd memory cells, setting coupling resistance values between bit lines and page buffers, and controlling sense control transistors to precharge and sense bit lines, thereby adjusting the coupling resistance value to reduce the width of threshold voltage distribution and minimize interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of threshold voltage distribution is increased due to interference phenomena, then more memory cells can be programmed, but read operation errors increase and read margin becomes insufficient
Solution Approach 1:
The patent segments the bit lines into even and odd bit lines, and divides memory cells into even and odd pages accordingly. This segmentation allows independent control and sensing of different cell groups, enabling the system to manage threshold voltage distribution more effectively and maintain read margins while programming multiple cells.
Solution Approach 2:
The patent applies different coupling resistance values to different bit lines (even vs odd) based on their specific characteristics and program states. By tailoring the coupling resistance locally to each bit line's conditions, the system optimizes read operations for each group, reducing errors while maintaining overall programming capability.
2Reliability
If coupling resistance value between bit line and page buffer is increased, then read operation stability improves, but sensing speed decreases
Solution Approach 1:
The patent dynamically adjusts the coupling resistance value between bit lines and page buffers based on the specific conditions of even and odd bit lines. The coupling resistance is not fixed but varies according to program states and interference levels, allowing the system to optimize between stability and speed for each operational context.
Solution Approach 2:
The patent changes the coupling resistance parameter adaptively based on the operational state. By modifying this key parameter according to whether even or odd bit lines are being sensed and their respective program states, the system achieves optimal performance for each scenario without compromising overall reliability or speed.
Data Source
AI summary
A method of operating a nonvolatile memory device includes determining whether a program operation is performed on even memory cells coupled to even bit lines of a selected page, setting a coupling resistance value between odd bit lines of the selected page and page buffers depending on whether the program operation for the even memory cells is performed, performing a program operation on the odd memory cells coupled to the odd bit lines, and coupling the odd bit line to the page buffer based on the set coupling resistance value and performing an verification operation for verifying whether threshold voltages of the odd memory cells on which the program operation is performed are a target voltage or more.