Memory Subsystem CRC Multiplexing for High-Speed Error Detection

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Solution Overview

Problem

Memory subsystems are susceptible to errors due to increasing transfer rates and decreasing voltage swings, which can cause computing system malfunctions, and existing error correction methods are inadequate.

Innovation Solution

Implementing cyclic redundancy code (CRC) schemes for both write and read operations within memory subsystems, using existing DRAM form factors without adding pins, by adding user intervals to data frames and multiplexing CRC bits over preexisting pins, allowing for error detection and correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction codes are added to memory subsystems, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvememory error detection and correctionVSAvoidmemory subsystem complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines CRC calculation and verification functions into the existing memory controller and memory device architecture, integrating error detection capabilities without adding separate dedicated hardware blocks. The CRC bits are calculated alongside data bits during normal memory operations, merging error detection with standard read/write cycles.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The memory controller and memory devices are designed to perform multiple functions: standard data transfer, CRC calculation, CRC verification, and error correction. The same hardware resources are utilized for both normal operations and error detection, making the system multi-functional without requiring separate dedicated error detection hardware.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If transfer rates are increased and voltage swings decreased, then memory performance is improved, but error susceptibility increases

Engineering Contradiction:

Improvememory transfer rateVSAvoidmemory error rate

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms where CRC bits are calculated and verified during memory read/write operations. When errors are detected through CRC verification, the system can request retransmission or trigger error correction codes to fix the data, creating a feedback loop that maintains reliability even at high transfer rates and low voltage swings.

Inventive Principle:

Principle #23Feedback

3Reliability

If CRC bits are added to data frames, then error detection capability is improved, but data transmission time increases

Engineering Contradiction:

Improveerror detection capabilityVSAvoiddata transmission time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary action by calculating CRC bits during the data write operation before the actual data transmission begins. The CRC bits are prepared in advance and transmitted alongside the data, so that when the data is read back, the verification can be performed immediately without requiring additional separate verification steps that would extend transmission time.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8132074B2Reliability, availability, and serviceability solutions for memory technology

Publication Date: 2012.03.06 TAHOE RES LTD

AI summary

Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.