Memory Subsystem CRC Framing for High-Speed Error Detection
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Solution Overview
Problem
Memory subsystems are susceptible to errors due to increasing transfer rates and decreasing voltage swings, which can cause computing systems to malfunction, and existing error correction methods are inadequate.
Innovation Solution
Implementing cyclic redundancy code (CRC) schemes for both write and read operations within memory subsystems, using existing DRAM form factors without adding pins, by adding user intervals to data frames and multiplexing CRC bits over preexisting pins, allowing for error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transfer rates are increased and voltage swings are decreased, then productivity is improved, but reliability deteriorates due to increased memory errors
Solution Approach 1:
The patent applies preliminary action by generating CRC check bits before data is written to memory. The CRC logic circuit computes check bits from the data bits and stores them alongside the data in memory cells. This pre-computed redundancy is then used during read operations to detect and correct errors that occur due to high transfer rates and low voltage swings, thus maintaining reliability while enabling high productivity.
Solution Approach 2:
The patent introduces CRC check bits as an intermediary element between the data bits and the error detection/correction process. These check bits serve as a mediator that carries error detection information without interfering with the original data. During read operations, the CRC logic circuit uses these check bits to identify and correct errors, thus protecting the data transmission reliability while maintaining high transfer rates.
2Reliability
If error correcting codes are implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the CRC logic circuit functionality into the memory subsystem architecture, combining error detection/correction capabilities with the existing memory read/write operations. The CRC logic circuit is integrated to work seamlessly with the memory controller, allowing error checking to be performed as part of the normal memory access operations rather than as a separate complex process. This integration reduces overall device complexity while maintaining reliability.
Solution Approach 2:
The patent changes the parameter representation by using CRC check bits instead of more complex error correcting codes. The check bits are generated based on specific CRC algorithms (such as CRC-4 or CRC-10) that provide adequate error detection capability with minimal overhead. This parameter change in the error detection mechanism maintains reliability while avoiding the complexity of full ECC implementations.
3Reliability
If CRC bits are added to data frames, then reliability is improved, but loss of time increases due to additional processing
Solution Approach 1:
The patent ensures continuity of useful action by performing CRC check bit generation during the data write operation itself, rather than as a separate preprocessing step. The CRC logic circuit computes check bits concurrently with data storage, and during read operations, the verification process is integrated into the normal data retrieval workflow. This continuous integration minimizes additional processing time while maintaining error detection capability.
Solution Approach 2:
The patent applies partial action by using selective CRC checking based on the specific memory operation and error probability. The system can adjust the level of CRC verification performed depending on the operational context, applying full error checking only when necessary. This partial application of error detection maintains reliability for critical operations while reducing time loss for routine operations where errors are less likely.
Data Source
AI summary
Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.