Memory Controller CRC Segmentation for Bandwidth-Efficient Error Checking
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Solution Overview
Problem
Current information handling systems (IHS) face inefficiencies due to the overhead of cyclic redundancy check (CRC) error checking, which incurs memory channel bandwidth loss, latency, and power consumption, especially when applied universally across all data transmissions.
Innovation Solution
Implementing a method to selectively enable CRC error checking based on memory access requests, where critical data is subjected to CRC and non-critical data is not, using a memory controller and system memory with CRC tables to differentiate between critical and non-critical memory portions, thereby reducing unnecessary error checking overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRC error checking is applied to all data transmissions, then data transmission reliability is improved, but memory channel bandwidth is lost and latency increases
Solution Approach 1:
The patent applies CRC error checking selectively to specific memory regions based on their criticality. Critical memory regions (e.g., those storing kernel data, device drivers, or safety-critical information) have CRC enabled, while non-critical regions (e.g., temporary buffers, cache data) have CRC disabled. This local differentiation allows the system to maintain high reliability where needed while preserving bandwidth in less critical areas.
Solution Approach 2:
The memory system is segmented into multiple regions with different error checking requirements. The patent divides the address space into critical and non-critical segments, allowing independent error checking policies for each segment. This segmentation enables the system to apply CRC only to necessary portions of memory, reducing overall overhead while maintaining data integrity for critical information.
2Reliability
If CRC error checking is applied to all data transmissions, then data transmission reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements power-efficient error checking by enabling CRC only in memory regions where data integrity is critical. By disabling CRC in non-critical regions, the system reduces the computational overhead and power consumption associated with error checking operations, while still maintaining reliability for important data transmissions.
3Reliability
If CRC error checking is applied to all data transmissions, then data transmission reliability is improved, but latency increases
Solution Approach 1:
The patent reduces latency by applying CRC error checking only to critical memory regions rather than all memory accesses. Time-sensitive operations accessing non-critical data can proceed without CRC overhead, while critical data transmissions maintain full error checking. This selective approach minimizes the average latency impact while preserving reliability where it matters most.
Data Source
AI summary
A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.