Memory Write Path CRC Checking for High-Speed Data Reliability
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Solution Overview
Problem
As semiconductor memory devices operate at increased speeds, errors in data transmission to memory devices become more likely, reducing data reliability and requiring effective error detection and prevention mechanisms.
Innovation Solution
A method and memory device that receive serial data and cyclic redundancy check (CRC) codes, convert them to parallel formats, calculate CRC codes, and compare them for error detection, outputting an error signal to either block or allow writing to the memory cell array based on the presence of errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating speed of memory device is increased, then the performance of semiconductor system is improved, but errors in data transmission are more likely to occur
Solution Approach 1:
The patent applies preliminary action by performing error detection through CRC code calculation and comparison before the data is written to the memory cell array. The received serial data and CRC code are converted to parallel format, the CRC code is calculated from the data, and the calculated CRC code is compared with the received CRC code to detect errors before memory writing occurs. This prevents erroneous data from being stored, thereby maintaining data reliability even at high operating speeds.
2Reliability
If error detection mechanism is added, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by integrating multiple functions into existing memory device components. The data parallel circuit performs both data format conversion (serial to parallel) and error detection (CRC calculation and comparison). The control circuit uses the error detection result to control the write operation, combining error detection and write control functions. This multi-functional integration achieves reliable error detection without significantly increasing overall device complexity.
3Productivity
If serial data is converted to parallel data for processing, then processing speed is improved, but additional circuit complexity is introduced
Solution Approach 1:
The patent applies merging by combining the serial-to-parallel conversion function with the error detection function in a single data parallel circuit. The same circuit that converts serial data and CRC code to parallel format also performs the CRC code calculation and comparison operations. This consolidation achieves high processing speed through parallel operations while minimizing additional circuit complexity by reusing the conversion circuitry for error detection purposes.
Data Source
AI summary
A method for operating a memory device is disclosed. The method includes receiving a serial data and a serial cyclic redundancy check (CRC) code transmitted sequentially through a channel, converting the serial data into a parallel data and the serial CRC code into a parallel CRC code, outputting the parallel data at a first time point, outputting the parallel CRC code at a second time point later than the first time point, calculating a CRC code by using the parallel data, comparing the parallel CRC code and the calculated CRC code with each other and detecting an error of the serial data transmitted through the channel according to the result of the comparison, and outputting an error detection signal in response to the result of the comparison.