Memory-Array Crossbar Computing for MIMO Matrix Operations
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Solution Overview
Problem
The existing processor-memory architecture is bottlenecked by the physical interface, limiting overall system performance due to the need for iterative matrix calculations in applications like MIMO and massive MIMO, which require fast and efficient matrix operations.
Innovation Solution
Convert a memory array into a matrix fabric using resistive elements to perform matrix transformations, allowing for parallel computation of matrix operations through a matrix multiplication unit (MMU), which can handle complex numbers and operate in a non-volatile state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor-memory architecture is used for matrix operations, then the system can perform iterative calculations, but the physical interface becomes a bottleneck limiting overall system performance
Solution Approach 1:
The patent merges the processor and memory functions into a single memory array that can perform both storage and matrix operations. The memory array is configured to store matrix data and perform matrix transformations internally, eliminating the need for separate processor-memory interfaces and reducing communication bottlenecks.
Solution Approach 2:
The memory array is designed to serve multiple functions: it stores matrix data, performs matrix transformations, and outputs results. This multi-functional approach allows the same hardware structure to handle both data storage and computation, improving productivity while reducing device complexity.
2Adaptability or versatility
If iterative matrix calculations are performed in existing architectures, then complex operations like MIMO can be executed, but processing time and power consumption increase
Solution Approach 1:
The memory array performs matrix transformations continuously without requiring iterative processing. By configuring the memory array to execute matrix operations in parallel using its inherent structure, the system achieves continuous useful action that reduces processing time while maintaining the capability to handle complex MIMO operations.
Solution Approach 2:
The patent replaces the traditional mechanical/sequential processing approach with an analog-based matrix transformation approach. The memory array uses voltage distributions and resistance values to perform matrix operations physically, substituting sequential digital computation with parallel analog transformation, thereby reducing processing time.
3Power
If traditional processor-memory interfaces are used, then data can be transferred, but the interface limits overall system performance
Solution Approach 1:
The patent extracts the computation function from the traditional processor and integrates it directly into the memory array. This eliminates the need for data transfer between processor and memory, removing the energy-consuming interface while maintaining or improving system performance.
Solution Approach 2:
The memory array serves itself by performing matrix transformations internally without requiring external processor intervention. This self-service capability reduces the need for energy-intensive data transfer interfaces while maintaining high system performance for matrix operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient, parallel matrix operations independent of matrix dimensions, reducing processing time and power consumption by leveraging non-volatile memory arrays, suitable for applications like MIMO and massive MIMO.
Implementation Method 1
each memory cell of the at least one array of memory cells is configured to store a digital value as an analog value in an analog medium
Implementation Method 2
perform matrix transformations, allowing for parallel computation of matrix operations through a matrix multiplication unit (MMU)
Data Source
AI summary
Methods and apparatus for performing diversity matrix operations within a memory fabric and for converting a memory array into a matrix fabric for spatial diversity-related matrix transformations and performing matrix operations therein. Exemplary embodiments described herein perform MIMO-related matrix transformations (e.g., precoding, beamforming, or data recovery matrix operations) within a memory device that includes a matrix fabric and matrix multiplication unit (MMU). In one variant, the matrix fabric uses a “crossbar” construction of resistive elements. Each resistive element stores a level of impedance that represents the corresponding matrix coefficient value. The crossbar connectivity can be driven with an electrical signal representing the input vector as an analog voltage. The resulting signals can be converted from analog voltages to a digital values by an MMU to yield a matrix-vector product. The MMU may additionally perform various other logical operations within the digital domain.