Semiconductor Memory Device Crossing-Point Training
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Solution Overview
Problem
High-speed semiconductor memory devices face challenges in maintaining opposite phases of differential data clocks due to noise-induced distortion and phase shifts during transmission, which affects data integrity and accuracy.
Innovation Solution
A semiconductor memory device and method that perform crossing-point training between differential data clocks, using a system clock and data clock input units to synchronize and phase-shift the data clocks, ensuring they maintain opposite phases through phase detection and training information signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential data clocks are transmitted through different transmission lines, then noise-induced distortion is reduced, but phase shifts occur due to resistance differences between transmission lines
Solution Approach 1:
The patent performs crossing-point training before normal data transmission to pre-adjust the phase of the second data clock. The memory device detects the logic level of the second data clock based on the edge of the first data clock and generates training information signals to shift the phase of the second data clock in advance, ensuring opposite phases are achieved before actual data transfer begins.
Solution Approach 2:
The patent implements a feedback mechanism where the memory device monitors the phase relationship between differential data clocks by detecting the logic level of the second clock based on the first clock's edge. Training information signals are generated and transmitted back to the memory controller to adjust the phase, creating a closed-loop system that ensures accurate phase alignment.
2Productivity
If a data clock with higher frequency is used to increase data input/output speed, then data transmission rate improves, but phase distortion increases due to noise
Solution Approach 1:
The patent divides the high-frequency data clock into two out-of-phase data clocks (first and second data clocks) that are transmitted differentially. This segmentation allows the system to maintain high data transmission rates while using differential signaling to reduce noise-induced phase distortion, as each clock line carries only one phase of the differential pair.
Solution Approach 2:
The patent introduces training information signals as an intermediary mechanism to mediate between the high-frequency data transmission requirements and phase stability. These signals enable the system to achieve and maintain accurate phase alignment despite the challenges of high-frequency operation and noise interference.
3Productivity
If two out-of-phase data clocks are transmitted simultaneously through different transmission lines, then data input/output capability is enhanced, but phase alignment becomes difficult to maintain
Solution Approach 1:
The patent performs crossing-point training before normal operation to pre-establish the correct phase relationship between the two data clocks. By detecting the logic level of the second data clock based on the first data clock's edge and generating appropriate training information signals, the system ensures that the clocks are properly aligned before data transmission begins, making the system easier to operate.
4Productivity
If the frequency of data clock is doubled to achieve four bits data input/output per system clock cycle, then processing speed increases, but the system becomes more sensitive to noise
Solution Approach 1:
The patent segments the high-frequency data clock into two differential clocks operating at half the frequency of the original single clock. This allows four bits of data to be transmitted per system clock cycle (two bits per edge) while reducing noise sensitivity, as the lower frequency differential clocks are less susceptible to noise-induced phase distortion.
Data Source
AI summary
A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.