Nonvolatile Memory Crosstalk Mitigation Using Combinational Logic
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Solution Overview
Problem
Nonvolatile memory systems suffer from crosstalk errors due to the influence of neighboring memory cells, which can cause data read inaccuracies and reduce reading throughput, especially in high-density arrays, and existing mitigation methods are complex and limit achievable throughput.
Innovation Solution
Implementing combinational logic within the memory device to read target memory cells multiple times and a neighboring cell once, using the readouts to determine output bits and confidence levels, compensating for voltage shifts caused by crosstalk, thereby improving ECC decoding success and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing crosstalk mitigation methods are implemented, then data read accuracy is improved, but device complexity increases and reading throughput decreases
Solution Approach 1:
The patent extracts only the essential information needed for crosstalk mitigation by reading neighbor memory cells once to generate a single neighbor binary readout, rather than performing multiple complex readings. This extracted neighbor readout is then used in combinational logic to correct target cell readings, achieving crosstalk mitigation with minimal additional complexity.
Solution Approach 2:
The patent segments the crosstalk mitigation process into distinct functional components: (1) reading target memory cells multiple times to produce target binary readouts, (2) reading neighbor memory cells once to produce a neighbor binary readout, and (3) applying combinational logic to combine these readouts. This segmentation allows each component to be optimized independently, reducing overall system complexity.
2Measurement precision
If existing crosstalk mitigation methods are implemented, then data read accuracy is improved, but reading throughput decreases
Solution Approach 1:
The patent applies partial action by reading neighbor memory cells only once instead of multiple times, and by using a simplified combinational logic approach rather than exhaustive error correction. This partial mitigation is sufficient to handle crosstalk effects while maintaining high reading throughput, as it performs only the minimum necessary corrections.
Solution Approach 2:
The patent replaces complex iterative error correction algorithms with a direct combinational logic system that processes target and neighbor binary readouts in a single pass. This substitution of mechanical/computational complexity with streamlined logic circuits enables fast throughput while maintaining accuracy.
3Measurement precision
If multiple target binary readouts are performed, then crosstalk mitigation accuracy is improved, but power consumption increases
Solution Approach 1:
The patent performs multiple readings of target memory cells (excessive action relative to single reading) to improve detection accuracy, but compensates by performing only a single reading of neighbor memory cells (partial action). This asymmetric approach optimizes power consumption by focusing multiple readings only where most needed while minimizing redundant readings.
Data Source
AI summary
A storage system includes circuitry and multiple memory cells. The memory cells are arranged in multiple Word Lines (WLs), including a target WL. The circuitry includes combinational logic implemented in hardware, the circuitry configured to: read a page from a group of target memory cells in the target WL multiple times to produce multiple respective target binary readouts, read a group of neighbor memory cells in a WL neighboring to the target WL so as to produce a single neighbor binary readout, apply the combinational logic to both the target binary readouts and the neighbor binary readout to produce (i) output bits of the page, and (ii) respective binary confidence levels associated with the output bits, and transmit the output bits and the binary confidence levels to a controller.