3D Memory Cube Packaging With Hybrid Bonding and Known-Good Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in efficiently bonding integrated circuit chips into three-dimensional packages due to limitations in redistributing contact areas and integrating high-density components, leading to increased manufacturing costs and reduced performance.
Innovation Solution
The formation of memory cubes through hybrid bonding of multiple memory devices with conductive bumps, followed by testing to ensure only known good cubes are used, and subsequent attachment to logic devices using reflowable connectors, allowing for improved electrical and thermal performance while reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If interposers are used to redistribute ball contact areas, then the area for contact distribution is increased, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent transitions from two-dimensional planar redistribution using interposers to three-dimensional vertical stacking architecture. Multiple memory devices are stacked vertically and bonded to a logic device, achieving contact distribution in the vertical dimension rather than requiring lateral area expansion through interposers. This reduces the footprint and simplifies the overall package structure.
Solution Approach 2:
The patent implements a nested architecture where memory devices are stacked vertically and integrated with the logic device in a hierarchical manner. The memory cubes are positioned above the logic device, creating a nested three-dimensional configuration that maximizes space utilization without requiring additional lateral area or complex interposer structures.
2Quantity of substance
If direct bonding of high-density integrated circuit chips is attempted, then integration density is improved, but bonding difficulty and manufacturing cost increase
Solution Approach 1:
The patent divides the high-density integration challenge into manageable segments by stacking multiple discrete memory devices vertically. Each memory device can be independently fabricated, tested, and bonded, reducing the complexity of bonding entire high-density chips directly. The segmentation allows for modular assembly and simplifies the bonding process while achieving high overall integration density.
Solution Approach 2:
The patent performs preliminary testing and validation of memory devices before final assembly into the three-dimensional package. Memory cubes are formed and tested separately, ensuring only functional units are integrated with the logic device. This preliminary action reduces bonding difficulties by pre-qualifying components and preventing defective assemblies.
3Adaptability or versatility
If three-dimensional packaging with multiple chips is implemented, then functionality and performance are improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple memory devices and a logic device into a single integrated three-dimensional package. The memory cubes are directly bonded to the logic device, combining storage and processing functions in one compact unit. This merging achieves enhanced functionality and performance while reducing the need for separate packages and interconnections, ultimately lowering overall manufacturing costs.
4Productivity
If defective memory cubes are processed further, then productivity is maintained, but reliability and performance decrease
Solution Approach 1:
The patent implements preliminary testing of memory cubes at intermediate stages of fabrication, forming memory cubes and testing them before final assembly with the logic device. This preliminary action identifies and isolates defective units early in the manufacturing process, preventing further processing of defective cubes while maintaining overall productivity by allowing continuous manufacturing of good units.
Solution Approach 2:
The patent extracts and removes defective memory cubes from the manufacturing stream through intermediate testing and selection processes. Only known good memory cubes are advanced to final assembly with the logic device, ensuring high reliability while maintaining productivity by continuously processing and testing units through the manufacturing pipeline.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical and thermal performance of memory cubes and reduces manufacturing costs by avoiding processing of defective memory cubes and utilizing cost-effective reflowable connectors for attachment to logic devices.
Implementation Method 1
The formation of memory cubes through hybrid bonding of multiple memory devices with conductive bumps
Implementation Method 2
subsequent attachment to logic devices using reflowable connectors
Data Source
AI summary
In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.